verilog instantation and concatenation [duplicate]

Question

error reports on v 53,55,57 it says module instantiation should have an instance name how can I solve this problem?

my_adder is 32 bit adder, it's overflow is 1 bit. but overflow in adder_array is 4 bit. how can I solve this?

module adder_array(
     cmd,
     ain0, ain1, ain2, ain3,
     bin0, bin1, bin2, bin3,
     dout0, dout1, dout2, dout3,
     overflow);

    input [2:0] cmd;
    input [31:0] ain0, ain1, ain2, ain3;
    input [31:0] bin0, bin1, bin2, bin3;
    output reg [31:0] dout0, dout1, dout2, dout3;
    output [3:0] overflow;

    wire [31:0] a[3:0];
    wire [31:0] b[3:0];
    wire [31:0] d[3:0];
    wire ovf[3:0];

    assign {a[0],a[1],a[2],a[3]} = {ain0,ain1,ain2,ain3};
    assign {b[0],b[1],b[2],b[3]} = {bin0,bin1,bin2,bin3};
    assign {d[0],d[1],d[2],d[3]} = {dout0, dout1, dout2, dout3};


    parameter size = 4;

    genvar i;

    generate for(i = 0 ; i < size - 1 ; i = i + 1)
    begin: adder
        if (i == 0) begin
          my_add(.ain(a[0]), .bin(b[0]), .dout(d[0]), .overflow(ovf[0]));
          end
        else if (i == size - 1 ) begin
          my_add(.ain(a[i]), .bin(b[i]), .dout(d[i]), .overflow(ovf[i]));
          end
        else begin
          my_add(.ain(a[i]), .bin(b[i]), .dout(d[i]), .overflow(ovf[i]));
          end
    end
    endgenerate
    assign overflow = {ovf[3], ovf[2], ovf[1], ovf[0]};


    always @(cmd) begin
        case(cmd)
            3'b000 : begin dout0 = d[0]; dout1 = 0; dout2 = 0; dout3 = 0; end
            3'b001 : begin dout0 = 0; dout1 = d[1]; dout2 = 0; dout3 = 0; end
            3'b010 : begin dout0 = 0; dout1 = 0; dout2 = d[2]; dout3 = 0; end
            3'b011 : begin dout0 = 0; dout1 = 0; dout2 = 0; dout3 = d[3]; end
            3'b100 : begin dout0 = d[0]; dout1 = d[1]; dout2 = d[2]; dout3 = d[3]; end               
        endcase
    end

endmodule

Matthew · Accepted Answer · 2018-03-16 11:52:33Z

0

The error message is pretty clear. Instances of modules such as this:

my_add(.ain(a[0]), .bin(b[0]), .dout(d[0]), .overflow(ovf[0]));

need instance names, eg

my_add my_add0 (.ain(a[0]), .bin(b[0]), .dout(d[0]), .overflow(ovf[0]));
       ^^^^^^^

Instances of modules in Verilog must always have an instance name. An instance name is like a label on a circuit diagram. On a circuit diagram, you'd label ICs as IC1, IC2 etc, capacitors as C1, C2 etc. You need to do what is effectively the same thing in Verilog. And, just like on a circuit diagram, instance names must be unique with in a particular scope (ie within a module). The circuit diagram analogy still holds: you wouldn't have two IC1s or two C1s on a circuit diagram would you?

answered Mar 16, 2018 at 11:52

Matthew

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3 Comments

Isaac Kim Over a year ago

Thanks for your answer! But I want to make 4 my_add by using generate for statement, not by making my_add0, my_add1, my_add2. How can I do this?

Oldfart Over a year ago

You still have to give it a name.

Matthew Over a year ago

@IsaacKim as oldfart says. you've still got to give it a name. The hierarchical instance name of the instance in my example will end in .adder[i].my_add0, because adder is the name of the block in which my_add0 appears. Why are you adverse to naming it? A generate statement is merely a way of generating a (slightly) variable number of concurrent things, for example instances, initial/always blocks/assign statements.Try it and see what happens.

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