When reading about the MC6800 somewhere, I remember it being stated that a two-phase clock signal was used because it allowed the designers of the processor (as well as many other older MPUs) to use transparent latches instead of synchronous flip-flops in the register file. However, (since I'm still relatively new to the whole electronics thing) I can't quite imagine how using a two-phase clock would allow one to use latches in place of flip-flops. I tried googling it but to no avail. Could somebody please explain it to me? Thanks!
2 Answers
I suppose you read it in the Wikipedia article on clock signals, which is linked to in the Wikipedia article on the 6800:
In synchronous circuits, a "two-phase clock" refers to clock signals distributed on two wires, each with non-overlapping pulses. [...] Because the two phases are guaranteed non-overlapping, gated latches rather than edge-triggered flip-flops can be used to store state information so long as the inputs to latches on one phase only depend on outputs from latches on the other phase. Since a gated latch uses only four gates versus six gates for an edge-triggered flip-flop, a two phase clock can lead to a design with a smaller overall gate count but usually at some penalty in design difficulty and performance.
The "non-overlapping" and "level triggered" vs. "edge triggered" bits are important here.
In regular clocked logic, the computational results of clock cycle are transferred into registers at one edge of the clock, either rising or falling; you then have the entire next cycle for the next computational step. This requires edge-triggered flip-flops, which need 6 gates per bit to build.
Two phase logic lets you use the first phase of the clock for computation, then the whole second phase for storing, so you can use level-triggered flip-flops, or latches, tied to the second phase of the clock. Those only need four gates per bit. However, you need to slow down your clock a bit, as the entire computation now needs to fit into (roughly) the first phase. So you save about 33% of gates in your registers at the expense of running at about half the speed. Not a good trade-off these days, but a good one in the mid-70s, when chip real estate was your limiting factor.
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1"the entire computation now needs to fit into (roughly) the first phase" Not really. You just need to be able to split the computation into "even" and "odd" phases, sometimes adding an extra latch to get aligned to the correct phase at the output.Dave Tweed– Dave Tweed2025-10-27 18:03:46 +00:00Commented 13 hours ago
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@DaveTweed With a transparent latch, you either need to get done in the first phase; add a second latch (as you suggest), adding extra gates (which we're trying to minimize) and possibly an extra cycle; or be very careful about glitches propagating through the transparent latch ‒ or am I overlooking something?Michael Graf– Michael Graf2025-10-27 18:28:34 +00:00Commented 13 hours ago
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The phases are completely symmetrical. You can, for example, do the first half adder of a full adder on phase 1, latch the outputs of that, and do the second half adder on phase 2 and latch the outputs of that. You're just breaking a pipeline of operations into finer steps. The only limitation is that there needs to be an even number of steps overall, which is why you sometimes need an "extra" latch to line things up.Dave Tweed– Dave Tweed2025-10-27 20:38:58 +00:00Commented 11 hours ago
The flip-flop is already two latches running on different phases of the clock:
Natural for NMOS-era CPUs was to have pass-gate dynamic latches like this:
When the pass transistor open, the latch is transparent, when it closed, the latch keeps last value (with the obvious inversion at the output). Now if you supply two-phase clock to these two latches connected in series (φ1 and φ2), you'll get flip-flop functionality.
This basically shows the answer to the question; yet different CPUs have different means of getting two-phase clock. For i8080, there are two separate inputs, 6502 would make two-phase clock internally.
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I wonder how much it would have cost in various technlogies (TTL, NMOS, or CMOS) to have parts with edge-triggered clocks specify that a clock input will have separate thresholds for capturing inputs and propagating outputs--behavior equivalent to having one clock phase go high when the clock input is low, and the other go high when it's high, with a little forced dead time between? That would have ensured that when a signal is fed between devices that share a clock wire, the receiving device will capture the state that was being transmitted before the relevant clock edge so long as...supercat– supercat2025-10-27 18:20:53 +00:00Commented 13 hours ago
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...the clock rises or falls monotonically, and the 'change outputs' threshold on the sender doesn't change until after the 'capture inputs' threshold has been reached on the recipient.supercat– supercat2025-10-27 18:21:56 +00:00Commented 13 hours ago
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Point 1 is incorrect. An edge-triggered D-type flip-flop is NOT the same as two D-latches in a master-slave configuration. Furthermore, figure 2 should have a feedback inverter to hold the value stable. Pure capacitive storage was very rare, as it requires impractically large capacitors to hold data for more than a cycle or two.markai– markai2025-10-27 19:11:25 +00:00Commented 12 hours ago
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@markai: The two-latch circuit with clock inverter placed shown will act as a rising-edge-triggered flip-flop. While the clock is low, the output of the first latch will track the input. When the clock rises, the output of the second latch will switch to match that of the first latch, while the first latch will stop tracking the input. When the clock falls, the second latch will stop tracking the output of the first latch before the first latch starts tracking the input again. Other approaches of implementing an edge-triggered flop may have different setup, hold, and propagation times,...supercat– supercat2025-10-27 19:57:03 +00:00Commented 11 hours ago
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...and may behave differently if setup/hold times are violated, but if the data input doesn't change near rising clock edges I would think the behavior would match an edge-triggered flopflip-.supercat– supercat2025-10-27 19:57:56 +00:00Commented 11 hours ago