Incrementing a variable in for-generate in verilog

Question

I need to generate the following assignments in a for-generate block in verilog. This is a part of an signed number multiplication process for a given bit size n=8 bits.

assign p[1]=pp[1][1];
assign p[2]=pp[2][1];
assign p[3]=pp[3][1];
assign p[4]=pp[4][1];
assign p[5]=pp[5][1];
assign p[6]=pp[6][1];

assign p[7]=pp[7][1];
assign p[8]=pp[8][2];
assign p[9]=pp[9][3];
assign p[10]=pp[10][4];
assign p[11]=pp[11][5];
assign p[12]=pp[12][6];
assign p[13]=pp[13][7];
assign p[14]=pp[14][8];
assign p[15]=pp[15][9];

I could write the first part in first conditional statement within the for loop. For the second if block I am not able to run the second index variable of the pp[][] array. How to do this?

genvar k;
generate
for(k=1; k<=2*size-1; k=k+1)
begin:product
    if (k<=size-2) begin
        assign p[k] = pp[k][1];
    end
    else if (k>size-2) begin
         assign p[k] = ??????????????????; //How to assign p[7] to p[15]
    end
end
endgenerate

Kirill Bulygin · Accepted Answer · 2017-02-25 16:31:08Z

2

According to the pattern:

assign p[k] = pp[k][k-6];

(The loop is like a preprocessor anyway, no substraction will happen in hardware of course.)

answered Feb 25, 2017 at 16:31

Kirill Bulygin

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