Verilog - incrementing variable using buttons

Question

I'm actually trying for 3 days to make my code works. I have an dev board with multiplexed 7-seg display - it's working. The problem is, when I'm trying to increment a variable. I written code below:

assign buttons =  debouncedL  | debouncedR;

always @(posedge buttons or negedge RES) begin
    if(~RES) number <= 0;
    else if(debouncedL) number <= (number + 10);
    else if(debouncedR) number <= (number + 1);
end

And it's not working. When I'm pressing R button, variable is incremented by 1, but when I'm pressing L nothing happens. After changing positions of both else if, L button still not work and displayed number is toggling between 0000 and 0001 after pressing R button. It might be newbie question, but I can't find solution in book and on Internet. Can you help me? Thank you in advance.

How is your FPGA toolkit actually implementing this? I'm drawn to think that your odd trigger logic might be making it more difficult to synthesize this than a synchronous design. — nanofarad
– nanofarad, Commented May 26, 2016 at 19:16
You mean this? i.imgur.com/CbOXAmj.png Red line is debouncedL. DebouncedR is the second line entering OR gate. — Kma
– Kma, Commented May 26, 2016 at 19:50
And this is version from code posted (where else if with L button is first): i.imgur.com/nzTUOtR.png — Kma
– Kma, Commented May 26, 2016 at 19:57

FabienM · Accepted Answer · 2016-05-27 07:05:29Z

Your design is asynchronous, you have metastability on buttons signal.

In synchronous design (and all FPGA design should be synchronous) only clock can be used for always @posedge() process. In your design you are using button signal as a clock.

To detect raising edge on button you have to save the old state of button signal and compare it to current state like this :

always @(posedge clock or posedge rst) begin
    // detect rising edge
    if (button_old != button && button == 1'b1)
          button_raise <= 1'b1
    button_old <= button;
    // increment number
    if(button_raise == 1b'1)
    begin
        if(~RES) number <= 0;
        else if(debouncedL) number <= (number + 10);
        else if(debouncedR) number <= (number + 1);
    end
end

Collectives™ on Stack Overflow

Verilog - incrementing variable using buttons

1 Answer 1

Comments

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Related