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So, I'm trying to interference three oscillated input of JKFF.

Resulting this: enter image description here

Performing AND interference between hypothetic phase shift 45 degree and No phase shift resulting this new pulse-width signal (GREEN): enter image description here

What is the new pulse-width value of green signal? Is it 33%? Or 25%? Or none of them?

PS: all of phase shift are unconfirmed, it's just based on perspective of oscilloscope. I don't know the absolute value of the phase shift.

I tried simulating it in C:

#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <inttypes.h>

#define PROGRAM_DURATION 100000000 // Program duration in CPU cycles

// Function to read the time-stamp counter: (faster than clock_gettime) because direct access to the CPU cycle counter
static inline uint_fast64_t rdtsc(void) {
    uint_fast32_t lo, hi;
    __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
    return ((uint_fast64_t)hi << 32) | lo;
}

static inline uint_fast8_t bit_set_to(uint_fast8_t number, uint_fast8_t n, bool x) {
    return (number & ~((uint_fast8_t)1 << n)) | ((uint_fast8_t)x << n);
}

// bool requires #include <stdbool.h> prior to C23
static inline bool bit_check(uint_fast8_t number, uint_fast8_t n) {
    return (number >> n) & (uint_fast8_t)1;
}

static uint_fast8_t SAMPLER[PROGRAM_DURATION]; // Sampler
static uint_fast32_t SAMPLER_INDEX = 0; // Sampler index
int main() {

    { // Quantum world

        register uint_fast8_t qubyte = 0; // Quantum byte

        // Initialize the core
        register uint_fast64_t NOW = rdtsc();
        register bool H = 0; // Hadamard Gate
        register bool S = 0; // Phase Gate (S) 90 degrees
        register bool T = 0; // Phase Gate (T) 45 degrees (UNCONFIRMED)
        const uint_fast64_t T_START = NOW;
        while (NOW - T_START < PROGRAM_DURATION) {
            H = bit_check(NOW, 2); // Update the Hadamard gate
            S = bit_check(NOW, 1); // Update the Phase gate (S)
            T = bit_check(NOW, 0); // Update the Phase gate (T)

            // Just apply based on my digital circuit design
            T &= S;
            T ^= H; 

            S ^= H;
            
            // =============QUANTUM RUNTIME==============
            // Quantum operations go here

            // Set the qubyte to H at bit index 5 with AND interference
            qubyte = bit_set_to(qubyte, 5, H & T);

            SAMPLER[SAMPLER_INDEX++] = qubyte; // Record the quantum state
            // ==========================================

            // Update the time-stamp counter
            NOW = rdtsc();
        }
    } // End of quantum world

    // Count non zero
    uint_fast32_t non_zero_count = 0;
    for (uint_fast32_t i = 0; i < SAMPLER_INDEX; i++) {
        if (SAMPLER[i] != 0) {
            non_zero_count++;
        }
    }

    // print non zero count ratio with sampler index
    printf("Non zero count ratio: %" PRIuFAST32 "/%" PRIuFAST32 "\n", non_zero_count, SAMPLER_INDEX);

    return 0;
}

Outputting:

Non zero count ratio: 674567/1798244 (about 37.5%)

Not sure, whether my simulation is wrong or not, but if it's true, 37.5% seems odd to me.

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1 Answer 1

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It is normal.

All signals use an 8x clock so d.f= 4/8 = 50%
0 AND 45 deg is reduced by 1/8 thus 3/8 = 37.5%

A clocked shift register is preferred rather than gating JK's to reduce skew.

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