Questions tagged [instruction-set]
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        0 address instruction format for subtraction
                    Suppose we want to subtract (3-2) using the 0 address instruction format.The code will be
push 2
push 3
sub
or
push 3
push 2
sub
And what about other logical  instructions(NOT,AND,OR,XOR) , how can we ...
                
            
       
        
            
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        Assembly question ISA
                    I am studying for a exam in Computer Architecture and one of the exercises says this:
write the assembly code which calculates the equation of D=(A+B)/4+C.The ISA of the processor has the following ...
                
            
       
        
            
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        Does newer CPU includes instruction set for popular hash and crypto algorithms
                    I mean since the algorithms like SHA256, MD5, AES, RSA are so widely used, so do these kind of popular algorithm get their special instruction set hardwired in newer CPU ?
And if they do, how fast do ...
                
            
       
        
            
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        How does the BIOS teletype routine work?
                    I am writing an OS. I am not a computer scientist, I am a physicist, so my understanding of computing is limited enough that I don't yet know how to ask the right questions. I am looking for either a ...
                
            
       
        
            
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        How simple addition operation performed with just one instruction by BitBitJump?
                    According this:
https://en.m.wikipedia.org/wiki/One-instruction_set_computer
Its instruction has 3 operands, the meaning is: copy the bit addressed by a to the bit addressed by b and jump to the ...
                
            
       
        
            
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        How many operands does the NOP instruction have?
                    At first I thought it is obvious, since the NOP instruction does not have any operand, we say it is zero-operand instruction. But then looking on the zero-operand ...
                
            
       
        
            
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        Load Store Hazard
                    I recently had an interview to identify all of the hazards in the following instruction set. I was told by the interviewer that there was some hazard between instructions i3 and i4 and it's not a RAW ...
                
            
       
        
            
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        What is the reason or advantage of having special purpose status flags for the result of comparisons? [duplicate]
                    The C semantics treat the result of a comparison or any true/false operation as just an int ...
                
            
       
        
            
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        Is a CPU with a hybrid Instruction Set Architecture (ISA) possible?
                    Is it possible to (theoretically) develop a CPU having a hybrid ISA such that half of the cores in it use the x86 architecture and the other half uses the ARM architecture? The x86 cores would run the ...
                
            
       
        
            
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        Learn computer architecture and organisation via an oversimplified machine
                    I wish to learn CO&A (computer organisation and architecture) from scratch via some toy system and its simulator. I found the following resource: Toy Machine developed at Princeton University.
Toy ...
                
            
       
        
            
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        Can a CPU instruction be split into 2 inputs?
                    Let's say there was a CPU with an input bus of 4 bits and the 4 bits are the opcode then the next 4 bits are the operand. It would just be an 8-bit instruction split in two. Is this possible and how ...
                
            
       
        
            
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        How does a CPU jump to a instruction thats no longer in ram?
                    Im designing my own CPU but I don't know how it jumps to an instruction that's no longer in ram. People have told me it puts the address in the SSD but for example, if the address were 3 in ram it ...
                
            
       
        
            
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        how to get the high 32-bit of the answer of two 32-bit integer multiple?
                    Recently, I study the instruction set of riscv32 and face a order as "mulh" which tends to multiply two 32-bits signed integers and store the high 32 value into the register.
And here comes ...
                
            
       
        
            
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        Is a specialized hardware instruction always faster than a software implementation, and if so, is there a general reason?
                    I started wondering this after reading about the x86-SSE instruction rsqrtss being faster (and more accurate) than the Fast inverse square root. I have also read ...
                
            
       
        
            
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        What is a procedure?
                    Non-computer scientist here, trying to understand what SICP (Structure and Interpretation of Computer Programs) means by a procedure, whether it matches the dictionary definition, and also how a ...
                
            
       
         
         
         
         
        