Questions tagged [cpu-pipelines]
The cpu-pipelines tag has no summary.
124 questions
0
votes
0
answers
41
views
Data Hazards and Stalls with Forwarding in a Pipelined CPU (MIPS-like Pipeline)
I am currently studying pipelined CPU architectures, specifically focusing on data hazards and forwarding. I have a question regarding stalls in a 5-stage pipeline with forwarding.
Consider the ...
- 1
0
votes
0
answers
31
views
Understanding the delays involved in fetching the correct target instruction on a branch mispredict
So I am going through an old research paper which talks about branch prediction strategies. The paper states the following on page 6:
Assume that for CPU, if instruction prefetches are based on a ...
0
votes
0
answers
47
views
Static two-issue RISC-V pipeline: how is this sd and blt data hazard handled?
I was following through this example (From the subheading Simple Multiple-Issue Code Scheduling in chapter 4.10 of
Computer Organization and Design RISC-V Edition by
Hennesy, Patterson), an example ...
- 1
2
votes
0
answers
41
views
How frequently would false dependencies occur without register renaming?
Given an out-of-order processor without register renaming, how frequently would false dependencies occur? I've been trying to find papers that actually measure this, but I have found nothing. AI ...
- 21
0
votes
0
answers
63
views
MIPS pipelined CPU Read and Write from Registers on First and Second Halves of Clock Cycle
In a pipelined MIPS CPU, writing to the pipeline registers, registers and PC occurs when the in the rising edge of the clock, and reading occurs in the falling edge, according to my understanding.
...
- 103
1
vote
1
answer
51
views
I1 writing back to memory, while I2 currently executing on value depended on I1. How is result coherency maintained?
question regarding OOE.
Imagine two instructions
mov %rax, [an_address} // I1
mov [an_address] %rbx // I2
I1 makes it into the execute stage of an intel CPU. And ...
- 13
2
votes
1
answer
118
views
Issue understanding how control signals are pipelined in a RISC architecture
I'm currently implementing a RISC prozessor in a HDL and realized that I seem to have a somewhat incorrect understanding of how pipeling works for control signals. Here's my general understanding:
...
- 21
2
votes
1
answer
196
views
1
vote
2
answers
95
views
Can a branch be pipelined with certainty if the branch condition can be known significantly before the actual branch?
A common issue with CPU performance is that pipelining requires the knowledge of what will come next, and what comes next can only be known once a branch condition is evaluated, so that instructions ...
- 209
0
votes
0
answers
64
views
Dependency in pipeline
Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the 4th instruction is an instruction whose operands depend on the result of the previous ...
2
votes
1
answer
487
views
Data hazard in MIPS: SW after ADD
Use the five-stage pipeline with forwarding unit.
add $t1, $t2, $t3
sw $t1, 0($t4)
In the above code, is the data hazard of t1 fixed by forwarding the correct t1 ...
- 21
4
votes
2
answers
2k
views
How efficient is register renaming?
As I understand, all modern CPUs perform register renaming: given a sequence of instructions to interpret, they check which registers these instructions use, detect patterns where a register's ...
1
vote
2
answers
351
views
What happens in harvard architecture pipelining if cpu needs to write data and fetch data at the same time?
What happens if Operand Fetch and Write Back happen in same cycle?
0
votes
2
answers
88
views
Formal proof for in-balanced pipeline throughput
It is a well known fact, the throughput of a given compute pipeline (say, CPU instruction pipeline) is determined by its "slow" segment.
All the resources I've seen so far, demonstrates this ...
- 101
0
votes
3
answers
586
views
Split an instruction into more than four sub instructions?
0
I am learning about the instructions-set in my computer science course, and I am wondering if it is possible to split an instruction into more than four sub-instructions.
Thank you
- 103