Unit I.pptx

Unit – I
Introduction to Computer
Organization

What is Computer?
• Computer is a programmable electronic device
designed to accept data, perform prescribed
mathematical and logical operations at high
speed and display the results of these operations.
• Computer is referred to as a system because it is
made up of integrated components like input,
output, storage and CPU, Which work together to
perform steps called for in the program being
executed.

Introduction to Computer
Organization and Architecture
Architecture Organisation
It refers to those attributes of a system
that are visible to the programmer and
have direct impact on logical execution
of a program.
 Logical Units
 Concepts that the system
programmer deals with directly like
Type of instructions, addressing
modes etc.
 Defines the system in an abstract
manner.
It refers to the operational units and
the interconnections between them
that achieve the architectural
specifications.
Physical Units
These concepts are transparent
from the programmer.
Realization of abstract model.
 ‘What’ does the system do/What
functionality is being provided?
‘How’ to implement the
functionalities that have been
provided by the architecture.

Functional Units and Components in
Computer Organization

Continued ……
• Main Memory/Memory is a place to store data and
instructions temporarily.
• Central Processing Unit: -
 ALU is a part of processor. ALU is responsible for executing
arithmetic and logical operations.
 Registers is faster than Main Memory. It is made up of Flip-
Flops (a bistable multivibrator).
 Control Unit generates Timing Signals (for controlling
Sequence of execution of instructions) and Control Signals
(for Controlling Read-Write operations in registers).

Continued …
• Input-Output Components: -
Input Module: Consists of same basic
components that accept data and instructions
in some form and connect them into an
internal form of signals usable by system.
Output Module: it serves as a medium for
displaying the results.

Continued…
• Buses:
In computer Architecture, a bus is a
communication system that transfers data
between components inside a computer, or
between computers.
A bus is a series of lines that connect the
processor to another part of the computer’s
architecture such as cache memory or main
memory.

Continued…
• Address Bus: Carries memory addresses from the
processor to other components such as primary
storage and input/output devices. The address bus is
unidirectional.
• Data Bus: carries the data between the processor and
other components. The data bus is bidirectional.
• Control Bus: carries control signals from processor to
other components. The control bus also carries the
clock’s pulses. The control bus is unidirectional.

Von Neumann Architecture/ Princeton Architecture
• It is a Computer architecture based on 1945 description
by John Von Neumann.
• Almost all computer designs are based on the concepts
developed by John Von Neumann. Such Designs are
referred to as Von Neumann Architecture.
• The 3 main Concepts: -
1) Data and instructions are stored in a single read-write
memory.
2) The contents of this memory are addressable by location
irrespective of the type of data or instruction present
there.
3) Execution occurs in a sequential manner from one
instruction to the next, unless changed explicitly.

Harvard Architecture
• The Harvard architecture is a computer architecture with
physically separate storage for instructions and data.
• In a computer using the Harvard architecture, the CPU can
read both an instruction and perform a data memory access
at the same time, even without a cache.
• A Harvard architecture computer can thus be faster for a
given circuit complexity because instruction fetches and data
access do not contend for a single memory pathway.
• In some systems, instructions can be stored in read-only
memory while data memory generally requires read-write
memory.

Von Neumann Architecture Vs
Harvard Architecture
Von Neumann Architecture Harvard Architecture
Single memory to be shared by
both instruction and data.
Separate memory for both
instruction and data.
Only one data bus used for
both data and instructions
Separate buses for both
instructions and data.
CPU can perform only one
operation at a time.
CPU can perform more than
one operation at a time.
2 set of clock Cycle required.
(1 cycle for data fetch & 1 Cycle
for instruction fetch)
Single Set of clock cycle is
sufficient.
Pipelining is not possible. Pipelining is possible.
Simple in design Complex in design.

Computer Registers
• In Computer Architecture, the Registers are very fast
computer memory which are used to execute
programs and operations efficiently. This does by
giving access to commonly used values, i.e., the
values which are in the point of operation/execution
at that time. So, for this purpose, there are several
different classes of CPU registers which works in
coordination with the computer memory to run
operations efficiently.
• The sole purpose of having register is fast retrieval of
data for processing by CPU. Though accessing
instructions from RAM is comparatively faster with
hard drive, it still isn’t enough for CPU.

Computer Registers
• Computer instructions are normally stored in consecutive
memory locations and are executed sequentially one at a
time. The control reads an instruction from a specific
address in memory and executes it. It then continues by
reading the next instruction in sequence and executes it,
and so on. This type of instruction sequencing needs a
counter to calculate the address of the next instruction
after execution of the current instruction is completed. It is
also necessary to provide a register in the control unit for
storing the instruction code after it is read from memory.
The computer needs processor registers for manipulating
data and a register for holding a memory address.

Different types of registers that are
present in the CPU
Note:-
 word is the unit
that a machine uses
when working with
memory. A word is a
fixed-sized piece of
data handled as a
unit by the
instruction set of
the hardware of the
processor.

Continued…
Register Name Symbol Number of bits Function
Address Register/
Memory Address
Register
AR/MAR 12 Holds address for the memory
location
Data Register/
Memory Data Register
DR/MDR 16 Holds the operand read from the
memory location
Accumulator AC 16 Processor Register/general purpose
processing register
Instruction Register IR 16 Holds instruction code
Program Counter PC 12 hold the address of the next
instruction to be read from
memory after the current
instruction is executed.
Temporary Register TR 16 Holds temporary data
Input Register INPR 8 Carries input characters
Output Register OUTR 8 Carries output character

Continued…
• The memory unit has a capacity of 4096 words
and each word contains 16 bits. Twelve bits of
an instruction word are needed to specify the
address of an operand.(we need 12 bits to
specify an address since 212 = 4096.) This
leaves three bits for the operation part of the
instruction and a bit to specify a direct or
indirect address.

Continued…
• The data register (DR) holds the operand read from memory.
• The accumulator (AC) register is a general purpose processing register.
• The instruction read from memory is placed in the instruction register
(IR).
• The temporary register (TR) is used for holding temporary data during the
processing.
• The memory address register (AR) has 12 bits since this is the width of a
memory address.
• The program counter (PC) also has 12 bits and it holds the address of the
next instruction to be read from memory after the current instruction is
executed.
• Two registers are used for input and output.
• The input register (INPR) receives an 8-bit character from an input device.
• The output register (OUTR) holds an 8-bit character for an output device.

Common Bus
System
The connection of
the registers and
memory of the
basic computer to
a common bus
system is shown in
figure.

Common Bus System
• The basic computer has eight registers, a memory unit, and a
control unit. Paths must be provided to transfer information
from one register to another and between memory and
registers. These registers and memory are connected to the bus
by some arrangements. The number of wires will be excessive if
connections are made between the outputs of each register and
the inputs of the other registers. A more efficient scheme for
transferring information in a system with many registers is to use
a common bus.
• The outputs of seven registers and memory are connected to
the common bus. The specific output that is selected for the bus
lines at any given time is determined from the binary value of
the selection variables S1, S2, and S0.

Continued…
• The number along each output shows the decimal
equivalent of the required binary selection. For
example, the number along the output of DR is 3. The
16-bit outputs of DR are placed on the bus lines when
S2S1S0 = 0 1 1 since this is the binary value of decimal 3.
The lines from the common bus are connected to the
inputs of each register and the data inputs of the
memory. The particular register whose LD (load) input
is enabled receives the data from the bus during the
next clock pulse transition. The memory receives the
contents of the bus when its write input is activated.
The memory places its 16-bit output onto the bus
when the read input is activated and S2S1S0 = 1 1 1 .

Continued…
• Four registers, D R , AC, IR, and TR, have 16 bits each. Two
registers, AR and PC, have 1 2 bits each since they hold a
memory address. When the contents of AR or PC are
applied to the 16-bit common bus, the four most significant
bits are set to O's. When AR or PC receive information from
the bus, only the 12 least significant bits are transferred
into the register. The input register INPR and the output
register OUTR have 8 bits each and communicate with the
eight least significant bits in the bus. INPR is connected to
provide information to the bus but OUTR can only receive
information from the bus. This is because INPR receives a
character from an input device which is then transferred to
AC . OUTR receives a character from AC and delivers it to an
output device. There is no transfer from OUTR to any of the
other registers.

Continued…
• The 16 lines of the common bus receive information from six
registers and
• the memory unit. The bus lines are connected to the inputs of six
registers and the memory.
• All these registers and memory are given certain signals.
• Memory will have 2 signals: read and write. Because in memory be
can perform only 2 operations i.e., either we can read from
memory or we can write to the memory.
• Five registers have three control inputs: LD (load), INR (increment),
and CLR (clear). (AR, PC, DR, AC and TR)
• Two registers have only a LD input. (IR and OUTR)
• LD means Load the register.
• INR means Increment the content of the register.
• CLR means Clear the data of that particular register or simply reset
the register.

Continued…
• INPR do not have any kind of signal because it
always connected to the input device and the
data coming from input device would be
stored in this INPR. It does not depend on any
kind of signal. It is asynchronous.
• All registers and memory except INPR are
connected to the clock because without the
synchronisation they can not work.

Continued…
• The input data and output data of the memory are connected to the
common bus, but the memory address is connected to AR . Therefore, AR
must always be used to specify a memory address. By using a single
register for the address, we eliminate the need for an address bus that
would have been needed otherwise. The content of any register can be
specified for the memory data input during a write operation. Similarly,
any register can receive the data from memory after a read operation
except AC .
• The 16 inputs of AC come from an adder and logic circuit. This circuit has
three sets of inputs. One set of 16-bit inputs come from the outputs of AC.
They are used to implement register micro operations such as
complement AC and shift AC . Another set of 16-bit inputs come from the
data register DR . The inputs from DR and AC are used for arithmetic and
logic micro operations, such as add DR to AC or AND DR to AC . The result
of an addition is transferred to AC and the end carry-out of the addition is
transferred to flip-flop E (extended AC bit). A third set of 8-bit inputs come
from the input register INPR.

Continued…
• Note that the content of any register can be applied onto the bus
and an operation can be performed in the adder and logic circuit
during the same clock cycle. The clock transition at the end of
the cycle transfers the content of the bus into the designated
destination register and the output of the adder and logic circuit
into AC . For example, the two micro operations
DR  AC and AC  DR
• can be executed at the same time. This can be done by placing
the content of AC on the bus (with S2S1S0 = 100), enabling the LD
(load) input of DR, transferring the content of DR through the
adder and logic circuit into AC, and enabling the LD (load) input
of AC, all during the same clock cycle. The two transfers occur
upon the arrival of the clock pulse transition at the end of the
clock cycle.

Computer Instructions
• A computer instruction is a binary code that
specifies a sequence of micro-operations for the
computer.
• The computer/CPU reads each instruction from
memory and places it in a control register.
• The control then interprets the binary code of the
instruction and proceeds to execute it by issuing
sequence micro-operations.
Note:-
 Program: A program is a set of instructions that specify the
operations, operands and the sequence by which processing has to
occur.

Instruction Code
• An instruction code is a group of bits that instruct the
computer to perform a specific operation.
• Instruction Format in Basic Computer:

Operation Code (Opcode)
• The operation code of an instruction is a group
of bits that define such operations as add,
subtract, multiply, shift, and complement.
• Unique binary code is assigned to every
OpCode, Which cannot be change.
• The number of bits required for the operation
code of an instruction depends on the total
number of operations available in the computer.
• The operation code must consist of at least n
bits for a given 2n (or less) distinct operations.

Instruction Format
• Example:
Here ADD is operation code and 457 is an address of operand in memory.

Direct Addressing
• If the second part of
an instruction format
specifies the address
of an operand, the
instruction is said to
have direct address.

Indirect Addressing
• In direct address, the
bits in the second part
of the instruction
designate an address of
a memory word in
which the address of
the operand is found.

Types of Computer Instructions
• In our system we are having 3 types of computer
instructions.
1. Memory Reference Instructions: These
instructions are going to deal with the memory
operands.
2. Register Reference Instructions: It will perform
certain operations onto the registers.
3. Input Output Instructions: Which performs
operations on input output devices.

Types of Computer Instructions

Register Reference Instruction

Instruction Set Completeness
• Instruction set is said to be complete if it
includes sufficient number of instructions in
each of the following categories:
1. Arithmetic, logical and shift instructions.
2. Instructions for moving information to and
from memory and processor registers.
3. Program control instructions together with
instructions that check status conditions.
4. Input and output instructions.

Instruction Cycle
• A program residing in the memory unit of the computer consists of
a sequence of instructions.
• The program is executed in the computer by going through a cycle
for each instruction.
• Each instruction cycle in turn is subdivided into a sequence of
subcycles or phases.
• In the basic computer each instruction cycle consists of the
following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an
indirect address.
4. Execute the instruction.
Note: -
this complete cycle is called as a machine cycle.

Fetch and Decode
• Initially, the program counter PC is loaded with the address of the
first instruction in the program.
• The sequence counter SC is cleared to 0, providing a decoded timing
signal T0. After each clock pulse, SC is incremented by one, so that
the timing signals go through a sequence T0, T1, T2, and so on.
• AR is connected to the address inputs of memory, it is necessary to
transfer the address from PC to AR during the clock transition
associated with timing signal T0.
T0 : AR  PC
• To provide the data path for the transfer of PC to AR we must apply
timing signal T0 to achieve the following connection:
1. Place the content of PC onto the bus by making the bus selection
inputs S2S1S0 equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of
AR .

Continued…
• The instruction read from memory is then placed in the
instruction register IR with the clock transition associated
with timing signal T1.
T1: IR  M[AR], PC  PC + 1
• At the same time, PC is incremented by one to prepare it
for the address of the next instruction in the program.
• it is necessary to use timing signal T1 to provide the
following connections in the bus system.
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making
S2S1S0 = 111.
3. Transfer the content o f the bus to IR by enabling the LD
input of IR .
4. Increment PC by enabling the INR input of PC.

Continued…
• At time T2, the operation code in IR is
decoded, the indirect bit is transferred to flip-
flop I, and the address part of the instruction
is transferred to AR.
T2: D0,....., D7  Decode IR(12-14),
AR  IR(0-11), I  IR(l5)

Determine the Type of Instruction
• The timing signal that is active after the decoding is T3. During
time T3, the control unit determines the type of instruction that
was just read from memory.
• The three possible instruction types available in the basic
computer.
• Decoder output D7, is equal to 1 if the operation code is equal to
binary 111.
• If D7 = 1, the instruction must be a register-reference or input-
output type.
• If D7 = 0, the operation code must be one of the other seven
values 000 through 110, specifying a memory-reference
instruction. Control then inspects the value of the first bit of the
instruction, which is available in flip-flop I.

Continued…
• If D7 = 0 and I = 1, we have a memory reference instruction with
an indirect address. It is then necessary to read the effective
address from memory.
ARM[AR]
• Initially, AR holds the address part of the instruction. This
address is used during the memory read operation. The word at
the address given by AR is read from memory and placed on the
common bus. The LD input of AR is then enabled to receive the
indirect address that resided in the 12 least significant bits of the
memory word.

Continued…
• The three instruction types are subdivided into four separate
paths. The selected operation is activated with the clock
transition associated with timing signal T3. This can be
symbolized as follows:
• D’7 IT3: AR  M [AR]
• D’7 I’T3: Nothing
• D7 I’T3: Execute a register-reference instruction
• D7IT3: Execute an input-output instruction

Unit I.pptx

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Unit I.pptx