fpga

Here are 3,676 public repositories matching this topic...

openwall / john

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

c fpga gpu opencl ripper assembler openmp mpi password hash simd gpgpu cracker john jtr crypt

Updated Jan 18, 2023
C

platformio / platformio-core

Star

A professional collaborative platform for embedded development 👽

Updated Feb 11, 2023
Python

PaddlePaddle / Paddle-Lite

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PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

arm mobile embedded fpga deep-learning neural-network mali baidu mdl mobile-deep-learning

Updated Feb 12, 2023
C++

logisim-evolution / logisim-evolution

Star

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Jan 31, 2023
Java

open-sdr / openwifi

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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Updated Feb 12, 2023
C

enjoy-digital / litex

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Build your hardware, easily!

fpga hardware system-on-chip

Updated Feb 10, 2023
C

LeiWang1999 / FPGA

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帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

SpinalHDL / VexRiscv

Star

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Feb 8, 2023
Assembly

jbush001 / NyuziProcessor

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GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Sep 11, 2022
C

openhwgroup / cva6

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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

asic cpu fpga risc-v systemverilog-hdl rv64gc ariane

Updated Feb 9, 2023
SystemVerilog

GlasgowEmbedded / glasgow

Star

Scots Army Knife for electronics

fpga usb hardware ice40 debugging-tool

Updated Feb 7, 2023
Python

darklife / darkriscv

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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu fpga core processor riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Dec 29, 2022
Verilog

FPGAwars / icestudio

Star

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

Updated Feb 10, 2023
JavaScript

clash-lang / clash-compiler

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Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Feb 10, 2023
Haskell

SpinalHDL / SpinalHDL

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Scala based HDL

scala fpga vhdl rtl verilog

Updated Feb 11, 2023
Scala

analogdevicesinc / hdl

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HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Feb 11, 2023
Verilog

sylefeb / Silice

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Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

language programming fpga

Updated Feb 10, 2023
C++

amaranth-lang / amaranth

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A modern hardware definition language and toolchain based on Python

fpga hdl yosys amaranth-hdl

Updated Feb 12, 2023
Python

stnolting / neorv32

Star

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.