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xilinx

Here are 532 public repositories matching this topic...

openwifi

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Updated Mar 16, 2023
C

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

pConst / basic_verilog

Must-have verilog systemverilog modules

Updated Mar 12, 2023
Verilog

hdl-util / hdmi

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

Updated Feb 3, 2023
SystemVerilog

Xilinx / brevitas

Brevitas: quantization-aware training in PyTorch

text-to-speech fpga pytorch speech-recognition neural-networks image-classification xilinx quantization hardware-acceleration brevitas

Updated Mar 26, 2023
Python

trabucayre / openFPGALoader

Universal utility for programming FPGA

fpga intel cyclone xilinx lattice bitstream arty gowin trenz-gowin-littlebee

Updated Mar 17, 2023
C++

prjxray

f4pga / prjxray

Documenting the Xilinx 7-series bit-stream format.

toolchain tools fpga xilinx vivado fuzzer xilinx-fpga bitstream artix7 artix kintex7 symbiflow

Updated Mar 25, 2023
Python

Cr4sh / s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

kernel fpga backdoor rootkit hypervisor uefi xilinx hyper-v dma microblaze pci-e

Updated May 26, 2021
C

ultraembedded / biriscv

Sponsor

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

trivialmips / nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

Updated Jul 7, 2020
SystemVerilog

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Mar 25, 2023
Python

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Feb 27, 2023
Verilog

eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga boom riscv xilinx vivado risc-v nexys-video vc707 rocketchip genesys2 kc705 arty-a7

Updated Mar 13, 2023
C

Vitis_Accel_Examples

Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Mar 20, 2023
Makefile

f32c / f32c

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

arduino fpga mips riscv xilinx altera lattice

Updated Mar 6, 2023
VHDL

bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

fpga driver xilinx zedboard axi-dma linux-driver axi-vdma dma-driver xilinx-axi-dma xilinx-axi-vdma userspace-dma fpga-dma

Updated Jan 12, 2023
C

Xilinx / SDAccel_Examples

SDAccel Examples

c aws fpga cpp opencl xilinx sdx sdaccel nimbix

Updated May 20, 2022
C++

ZipCPU / wb2axip

Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Updated Nov 14, 2022
Verilog

Xilinx / CHaiDNN

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

deep-neural-networks inference dnn xilinx alexnet googlenet embedded-vision xilinx-ultrascale-mpsocs

Updated Jul 9, 2019
C++

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