cornell-ece4750 / ece4750-tut3-verilog
ECE 4750 Tutorial 3: Verilog Hardware Description Language
| Aug | SEP | Oct |
| 02 | ||
| 2021 | 2022 | 2023 |

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ECE 4750 Tutorial 3: Verilog Hardware Description Language
This is a frequency divider model
Analogue Pocket Neogeo Core compatible with openFPGA
HDL libraries and projects
Verilog Ethernet components for FPGA implementation
Main Repository for the SimBricks Modular Full-System Simulation Framework.
Verilog AXI components for FPGA implementation
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Plugins for Yosys developed as part of the F4PGA project.
OpenROAD's unified application implementing an RTL-to-GDS Flow
The USRP™ Hardware Driver Repository
Re-coded Xilinx primitives for Verilator use
Must-have verilog systemverilog modules
PicoRV32 - A Size-Optimized RISC-V CPU