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asic-design

Here are 22 public repositories matching this topic...

chipsalliance / Cores-SweRV

SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Jan 27, 2022
SystemVerilog

google / qkeras

QKeras: a quantization deep learning library for Tensorflow Keras

machine-learning fpga deep-learning tensorflow accelerator keras quantization hardware-acceleration fpga-accelerator quantized-neural-networks asic-design quantized-networks

Updated Jul 25, 2022
Python

hughperkins / VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

machine-learning gpu verification verilog gpu-acceleration hardware-designs risc-v asic-design risc-v-assembly

Updated May 14, 2022
SystemVerilog

chipsalliance / Cores-SweRV-EL2

SweRV EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-el2 el2

Updated May 21, 2021
SystemVerilog

cpc / tce

Open Application-Specific Instruction Set processor tools (OpenASIP)

fpga hardware-designs asic-design hardware-accelerators

Updated Jul 19, 2022
C

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Jul 12, 2022
Verilog

lirui-shanghaitech / CNN-Accelerator-VLSI

Convolutional accelerator kernel, target ASIC & FPGA

fpga accelerator cnn fpga-accelerator cnn-digital cnn-accelerator asic-design

Updated Jun 21, 2021
Verilog

Lampro-Mellon / Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Updated Apr 13, 2021
Scala

dpretet / axi-crossbar

Sponsor

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 9, 2022
SystemVerilog

sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Oct 22, 2021
Verilog

JeffDeCola / my-systemverilog-examples

A place to keep my synthesizable SystemVerilog code snippets and examples.

simulator asic fpga hardware waveform verilog xilinx vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated May 13, 2021
Verilog

dpretet / friscv

Sponsor

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Aug 2, 2022
Coq

dpretet / bster

Sponsor

Implementation of a binary search tree algorithm in a FPGA/ASIC IP

asic fpga ip verilog binary-tree systemverilog binary-trees bst fpga-accelerator bstree asic-design svut

Updated Sep 5, 2021
SystemVerilog

rubinsteina13 / SV_I2S_RX_CORE

Synthesizable SystemVerilog IP-Core of the I2S Receiver

fpga verilog systemverilog hdl system-verilog cpld i2s i2s-dac ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

mnemocron / TSTE87

MATLAB code for the lab sessions in the "ASIC for DSP" course at LiU-ISY

asic signal-processing dsp fir-filter asic-design filter-theory fpga-design tste87

Updated May 11, 2022
MATLAB

andrsmllr / magic_vlsi_sky130_examples

Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.

asic examples layout vlsi vlsi-physical-design asic-design

Updated Mar 13, 2021

rubinsteina13 / SV_DSM_CORE

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

fpga verilog digital-signal-processing system-verilog cpld dac ip-core asic-design

Updated Jun 6, 2020
SystemVerilog

rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES

Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation

fpga verilog systemverilog digital-signal-processing digital-design cpld ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

opensilicon

erikvanzijst / opensilicon

Resources accompanying my talk at NLUUG 2022

fpga open-hardware risc-v conference-talk silicon asic-design

Updated May 13, 2022
HTML

Luca-Dalmasso / LL_contest

Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

vhdl tcl synopsys cmos low-power digital-electronics asic-design

Updated Jul 11, 2021
Verilog

Luca-Dalmasso / Microelectronic-systems

Laboratories of 'Microelectronic Systems' course at PoliTo

vhdl embedded-systems hardware-designs computer-architecture microprocessors digital-design microelectronics digital-electronics asic-design

Updated Jun 7, 2021
VHDL

vctrop / shapelet_distance_hardware_accelerator

Implementation and verification of the accelerator proposed in the paper "Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification", from May 2020

machine-learning hardware-acceleration normalization shapelets time-series-classification euclidean-distances asic-design shapelet-transform

Updated Apr 15, 2021
C

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