Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Updated
Oct 22, 2021 - Verilog
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systemrdl
Here are 11 public repositories matching this topic...
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
eda
verilog
systemverilog
uvm
registers
systemrdl
register-descriptions
systemrdl-compiler
fpga-development
asic-design
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Updated
Oct 22, 2021 - Verilog
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asic
fpga
verilog
rdl
systemverilog
hdl
registers
systemrdl
systemrdl-compiler
hardware-description-language
register-description-language
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Updated
Nov 27, 2021 - Python
SystemRDL lexer for Pygments syntax highlighting
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Updated
Dec 10, 2020 - Python
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