The Wayback Machine - https://web.archive.org/web/20210620034746/https://github.com/topics/yosys

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yosys

Here are 67 public repositories matching this topic...

m-labs / nmigen

Star

A refreshed Python toolbox for building complex digital hardware

fpga hdl yosys nmigen

Updated Feb 10, 2021
Python

nmigen / nmigen

Star

A refreshed Python toolbox for building complex digital hardware

fpga hdl yosys nmigen

Updated Jun 13, 2021
Python

cariboulabs / cariboulite

Star

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

radio rpi fpga pi software sdr raspberry icestorm rf yosys ice40 defined

Updated Jun 18, 2021
C

The-OpenROAD-Project / OpenLane

Star

NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Updated Jun 20, 2021
Verilog

olofk / edalize

Star

An abstraction library for interfacing EDA tools

Updated Jun 18, 2021
Python

nturley / netlistsvg

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draws an SVG schematic from a JSON netlist

visualization diagram elk yosys klayjs netlist

Updated Mar 29, 2021
JavaScript

zachjs / sv2v

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SystemVerilog to Verilog conversion

conversion verilog systemverilog yosys

Updated Jun 19, 2021
Haskell

forflo / yodl

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A VHDL frontend for Yosys

Updated Feb 27, 2017
C++

efabless / caravel

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Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Jun 18, 2021
Verilog

scarv / xcrypto

Star

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Mar 31, 2021
Verilog

dadamachines / doppler

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Arduino compatible – Cortex M4F & FPGA Development Board

arduino fpga icestorm yosys ice40 ice40up5k samd51

Updated Mar 22, 2019

ECP5-PCIe / ECP5-PCIe

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Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

fpga trellis yosys pcie ecp5 nextpnr prjtrellis nmigen gateware pcie-interface

Updated Apr 3, 2021
Python

mattvenn / fpga-sdft

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sliding DFT for FPGA, targetting Lattice ICE40 1k

fpga verilog fourier fft icestorm yosys sdft

Updated Apr 24, 2020
Verilog

fpga-tool-perf

SymbiFlow / fpga-tool-perf

Star

Open

Add FPGA interchange nextpnr implementation

1

litghost commented Feb 25, 2021

Initially only simple circuits will work, e.g. a counter. As more complicated circuit support is completed, add remaining circuits.

Read more

good first issue

Open

A single JSON file containing all meta.json data would be useful

1

Open

Add daveshah1's gameboy up5k-demo

sphinxcontrib-hdl-diagrams

SymbiFlow / sphinxcontrib-hdl-diagrams

Star

Sphinx Extension which generates various types of diagrams from Verilog code.

documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

Updated Apr 23, 2021
Python

tmeissner / psl_with_ghdl

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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Feb 20, 2021
VHDL

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Apr 27, 2021
Shell

tmeissner / formal_hw_verification

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Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Mar 13, 2021
VHDL

mmicko / enigmaFPGA

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Enigma in FPGA

fpga verilog yosys ice40 blackice goboard

Updated May 18, 2019
Verilog

YosysHQ / padring

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A padring generator for ASICs

asic eda chip vlsi yosys

Updated Jul 14, 2020
C++

yosys-symbiflow-plugins

SymbiFlow / yosys-symbiflow-plugins

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Plugins for Yosys developed as part of the SymbiFlow project.

toolchain fpga eda xilinx yosys xilinx-fpga symbiflow yosys-plugin

Updated Jun 18, 2021
C++

PyFPGA / pyfpga

Star

Open

Improve the Vivado block design example

rodrigomelo9 opened Feb 11, 2021

enhancement good first issue

Open

Verify windows support

4

YoWASP / yosys

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Unofficial Yosys WebAssembly packages

python fpga pypi webassembly yosys

Updated Jun 20, 2021
C

risc8

osresearch / risc8

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Mostly AVR compatible FPGA soft-core

microcontroller fpga yosys ice40 softcore upduino up5k

Updated Jul 31, 2020
Coq

scarv / scarv-cpu

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SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Apr 30, 2021
Verilog

akilm / Physical-Design

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Physical Design Flow from RTL to GDS using Opensource tools.

opensource raven chip yosys risc-v picorv32 physical-design pad-cells

Updated Nov 23, 2020

rodrigomelo9 / verifying-foss-hdl-synthesizers

Star

a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated Sep 26, 2020
Makefile

SymbiFlow / ibex-yosys-build

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Testing Ibex build using Yosys and open source toolchains.

riscv yosys risc-v ibex

Updated Jun 17, 2021
Shell

dadamachines / doppler-FPGA-firmware

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Bitstream src for doppler

docker dsp icestorm yosys risc-v ice40 i2s-audio ice40up5k

Updated Apr 12, 2019
C

anuejn / XC9500

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WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.

reverse-engineering digital-logic yosys cpld

Updated Aug 21, 2020
Python

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