Build software better, together

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Jul 27, 2020
Verilog

jfcherng-sublime / SublimeLinter-contrib-iverilog

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This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).

sublime-text sublimelinter linter-plugin verilog iverilog

Updated Nov 24, 2020
Python

pangguoming / iview-admin

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Vue 2.0 admin management system template based on iView 个人修改版

vue admin-dashboard iverilog

Updated Mar 1, 2018
JavaScript

JeffDeCola / my-systemverilog-examples

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A place to keep my synthesizable SystemVerilog code snippets and examples.

simulator asic fpga hardware waveform verilog xilinx vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated May 13, 2021
Verilog

rodrigomelo9 / verifying-foss-hdl-synthesizers

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a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated Sep 26, 2020
Makefile

patrickleboutillier / jcscpu-hw

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Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

fpga verilog vivado iverilog

Updated Aug 3, 2020
Verilog

pytec8800 / pint_iverilog

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Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

simulation rtl risc-v iverilog

Updated Nov 15, 2021
C++

OpenEDF / verilog-basic

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learn the combinational and sequential logic circuit.

simulator fpga simulation vhdl verilog iverilog ice40up5k fpga-programming

Updated Jul 28, 2022
Verilog

dpretet / meduram

Sponsor

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Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

a2k-hanlon / linter-veriloghdl

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Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

compiler linter slang verilog systemverilog hdl iverilog icarus verilator verible

Updated Apr 2, 2022
CoffeeScript

yasnakateb / PipelinedARM

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💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

strongwong / bittyCore_RISC-V

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This is a bitty CPU core of risc-v architecture, which is currently under development.

cpu verilog pipeline-processor risc-v iverilog rv32i bittycore

Updated Oct 23, 2020
Verilog

yasnakateb / Router

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👶🏻 My first baby steps into the world of NoC

router verilog icarus-verilog verilog-hdl iverilog

Updated Mar 14, 2022
Verilog

KiranThomasCherian / VLSI-and-Computer-Architecture

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Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

pipeline verilog xilinx floating-point computer-architecture vlsi hardware-modules adder wallace-tree-multiplier iverilog floating-point-arithmetic pipelined carry-propogate-adders kogge-stone-adder sklansky-adder magic-tool gate-layout cmos-path-enumerator

Updated May 8, 2021
Verilog

JacobLondon / SoftProcessorWatermark

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A MIPS softcore processor to average images together and output to VGA on a Nexys 4 DDR FPGA.

python opencv school fpga matlab verilog xilinx vivado vga iverilog mips-softcore-processor

Updated Aug 30, 2019
C++

arjunrajasekharan / 16bit-Sklansky-Adder

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16-bit Slansky Adder design using verilog HDL

verilog gtkwave vlsi testbench iverilog sklansky-adder

Updated May 14, 2021
Verilog

yasnakateb / PipelinedMIPS

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🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

cpu pipeline mips verilog icarus-verilog verilog-hdl iverilog mips-processor mips-pipeline

Updated Aug 30, 2020
Verilog

arjunrajasekharan / 16-bit-DADDA-Multiplier

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16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

compressor gtkwave vlsi testbench iverilog dadda-tree-multiplier

Updated May 14, 2021
Verilog

mshr-h / fibonacci_verilog

Sponsor

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fibonacci number calculator written in Verilog-HDL

fibonacci altera fibonacci-numbers verilog-hdl iverilog

Updated Feb 23, 2017
Verilog

ParimalaS27 / Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

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This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

verilog prefix icarus-verilog 8bit iverilog parallel-prefixsum prefix-adder ddco