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471 contributions in the last year
Contribution activity
October 2020
- [FIRRTL] Add ExtModule Verification
- [RTL] More Module cases
- [RTL] RTL module results as outputs
- [RTL] Add canonicalization pass for shift left.
- [FIRRTL] Add support for new Verification statements (assert, assume, cover)
- [FIRRTL] Add AsyncReset Parsing
- [FIRRTL] Add start of FIRRTL types lowering
- [RTL] Allow AnyType on RTL modules
- add rtl.extmodule to represent external modules.
- [StandardToHandshake] Remove ostream.
- [LLHD] Add most missing LLVM dialect lowerings
- [RTL] Add name attribute if ssa has an useful name
- [SV] Add SV Dialect operations to represent interfaces
- [ESI] Type System
- [RTL] Remove redundant condition
- [RTL] Use 'name' attributes for their SSA names
- Add comparison operators to the RTL dialect.
- [RTL] Allow RTL.Instances to be in any SymbolTable region
- [RTL] Factor out more of the flattening case in canonicalization pass.
- [rtl] Add flattening for `xor`, `or`, `add`, `mul`.
- [RTL] Add `xor`, `or`, `add`, `mul` constant folding.
- [FIRRTL] Verify that RegOp/RegInitOp are passive
- [RTL] Add `and` flattening case, `or`, `xor` idempotency case.
- [LLHD] Add folders for DrvOp and ExtractElementOp
- Generate docs for dialects
Created an issue in circt/node that received 5 comments
Let's talk about circt/node
Please propose new repos on the circt discourse forum before creating them. I think this should be in the main circt repo for a variety of reasons. A…
5
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