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[FIRRTL] Add ExtModule Verification #162

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merged 5 commits into from Oct 23, 2020

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@seldridge seldridge commented Oct 19, 2020

Adds checking of FIRRTL extmodule (FExtModuleOp) that brings the FIRRTL Dialect verification in line with the examples that I extracted from the Scala FIRRTL Compiler tests. A FIRRTL circuit is now verified such that the following properties hold:

  1. External module defnames will not conflict with module names
  2. External modules with the same defname must have the same port names with the same port types
  3. (2) is relaxed for external modules which have parameters in that they do not have to match on width

To help with this, this PR adds a method, getWidthlessType to FIRRTLType that sets all the widths to unknown to facilitate a check like this.

Towards #80.

@seldridge seldridge requested a review from darthscsi Oct 20, 2020
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@seldridge seldridge force-pushed the seldridge:firrtl-extmodule-verification branch from 4cb2253 to ba13215 Oct 21, 2020
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@lattner lattner left a comment

Looks nice assuming this is the correct semantics for the conflict check, thanks!

seldridge added 2 commits Oct 22, 2020
Add a method, getWidthlessType, to FIRRTLType that strips the widths
from that FIRRTLType. This is used in situations where you are trying
to do some structural equivalence of names and types, but don't want
to consider widths.

Signed-off-by: Schuyler Eldridge <[email protected]>
Adds verification of the FIRRTL Circuit operand to reject circuits
with invalid FExtModules. This checks the following things:

1. No FExtModule defname conflicts with an FModule symbol name

2. All FExtModules with the same defnames have the same number of
ports

3. All FExtModules with the same defnames have ports with the same
name in the same order.

4. All FExtModules with the same defname have exactly the same type of
port including widths if they take no parameters and exactly the same
type of port excluding widths if they take parameters.

Adds tests of the above behavior.

This aligns FIRRTL Dialect behavior to accept and reject the same
circuits that the Scala FIRRTL Compiler accepts and rejects in its
test suits that involve ExtModules.

Signed-off-by: Schuyler Eldridge <[email protected]>
@seldridge seldridge force-pushed the seldridge:firrtl-extmodule-verification branch from 9120de8 to 2941584 Oct 22, 2020
@github-actions github-actions bot requested a review from lattner Oct 22, 2020
@seldridge seldridge changed the title [FIRRTL] Add basic defname verification [FIRRTL] Add ExtModule Verification Oct 22, 2020
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@lattner lattner left a comment

cool, thank you for working on this!

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@lattner lattner left a comment

Nice, just a couple of suggestions to further simplify the code, thank you for implementing this!

// Go to next extmodule if no extmodule with the same defname
// was found.
if (!collidingExtModule)
continue;

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lattner Oct 23, 2020
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would it make sense to pull this into the 'if' above? Something like: if (!value) { value = extModule; continue }. This eliminates the "else" by making it be the fall through.

Just my personal style, but I wouldn't worry about adding the extra scope around the "value" reference. Once you do that, you can move the definition of collidingExtModule lower.

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seldridge Oct 23, 2020
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Yeah, it's cleaner to just move the continue up. I can also remove the scope guarding of value by just putting that in the if statement.

for (auto p : llvm::zip(ports, collidingPorts)) {
StringAttr aName, bName;
FIRRTLType aType, bType;
std::forward_as_tuple(std::tie(aName, aType), std::tie(bName, bType)) = p;

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lattner Oct 23, 2020
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Whoa, I've never seen forward_as_tuple before :-). I tend to use lower abstraction code for clarity, but this is fine.

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@seldridge seldridge merged commit 30beb96 into llvm:master Oct 23, 2020
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@seldridge seldridge deleted the seldridge:firrtl-extmodule-verification branch Oct 23, 2020
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@lattner lattner commented Oct 23, 2020

nice work!

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