#
vivado
Here are 210 public repositories matching this topic...
mithro
commented
Oct 10, 2019
Here is a simple example for Vivado.
def vivado_resources(self):
report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
with open(report_path, 'r') as fp:
report_data = fp.read()
repo
Open
About Doc and Readme
sinatv52
commented
Oct 24, 2018
Hello sir, may you please provide new and detailed doc and readme about this project?
This would be a great pleasure by you.
Best wishes.
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
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Updated
Nov 25, 2019 - SystemVerilog
HarrisonMc555
commented
Feb 5, 2019
I have a couple contributions to make to the documentation found at http://www.rapidwright.io/docs/. Is there place to submit these contributions?
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux
iot
fpga
zynq
tensorflow
assembly
vhdl
embedded-systems
internet-of-things
hardware-architectures
verilog
xilinx
vivado
tensor
hardware-designs
hardware-acceleration
fpga-accelerator
hardware-description-language
ip-core
tpu
-
Updated
Jan 5, 2019 - VHDL
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
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Updated
Apr 20, 2020 - Tcl
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
fpga
dsp
vhdl
verilog
fast-fourier-transform
xilinx
fft
vivado
altera
cooley-tukey-fft
digital-signal-processing
fast-convolutions
radix-2
integer-arithmetic
route-optimization
-
Updated
Apr 25, 2019 - VHDL
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
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Updated
Jan 30, 2020 - Tcl
Verilog Implementation of an ARM LEGv8 CPU
arm
verilog
xilinx
isa
vivado
hazard-detection
ldr
pipeline-cpu
single-cycle
hennessy
patterson
legv8-arm
multi-cycle
arm-legv8-simulator
forwarding-unit
-
Updated
Oct 3, 2018 - Verilog
mirror of https://git.elphel.com/Elphel/vdt-plugin
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Updated
Nov 29, 2017 - Java
Lenet for MNIST handwritten digit recognition using Vivado hls tool
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Updated
Mar 3, 2020 - Objective-C
Global Dark Mode for ALL apps on ANY platforms.
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Updated
Jun 28, 2020 - Verilog
a project to check the FOSS synthesizers against vendors EDA tools
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Updated
May 18, 2020 - Makefile
PYNQ DMA benchmark project
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Updated
Apr 27, 2017 - Tcl
16-bit Adder Multiplier hardware on Digilent Basys 3
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Updated
Apr 9, 2020 - Verilog
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557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used: