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systemverilog

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veripoolbot
veripoolbot commented Sep 1, 2019

Author Name: Enze Chi
Original Redmine Issue: 1495 from https://www.veripool.org


With verilog-mode from master branch (be9b5af)

I have 3 expression as below, after press , I got wrong alignment for the example code as below:

     startc_c         <= (valid && (state == THE_START));
     end_c             <= (valid && (state == THE_END));
     valid_c          
rafaelnp
rafaelnp commented Mar 14, 2020

Add command line option, to enable the user to choose which builder he/she wants to use. Suggestion:
--builder BUILDER specify the builded to be used

By adding it, it would allow:

  1. Users to actively choose the builder the way to use, without any code change (e.g. editing hdl_checker/builder_utils.py).
  2. to separate use cases and make it easier to track bugs that may arise.

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