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Leeor

Haifa

Programmer, CPU architect of sorts, performance analyst, PhD student, coffee connoisseur, and a proud father (n=3)

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Top Questions
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240
Difference between core and processor
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83
What's the difference between conflict miss and capacity miss
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63
GCC memory barrier __sync_synchronize vs asm volatile("": : :"memory")
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45
Why does the speed of memcpy() drop dramatically every 4KB?
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42
Physical or virtual addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3?
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32
Generate same unique hash code for all anagrams
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29
loop tiling. how to choose block size?
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26
How to write or read memory without touching cache
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23
Makefile:1: *** missing separator. Stop
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20
Haswell memory access
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20
Perl syntax compile error
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19
Given this same piece of code, why is the python version 100x+ slower than C?
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18
Branch target prediction in conjunction with branch prediction?
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16
Do compilers produce better code for do-while loops versus other types of loops?
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14
Do I need to free local variables?
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14
What are the fantasy secret hats you'd wish to get?
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14
Give new edit reviewers some audits to begin with
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14
When should we use prefetch?
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14
prefetching data at L1 and L2
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13
Trying to pass the output of echo into mkdir command
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13
Algorithm - find all permutations of string a in string b
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13
Cache specifications for intel core i7
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12
Does software prefetching allocate a Line Fill Buffer (LFB)?
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12
Difference between prefetch for read or write
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11
Why denormalized floats are so much slower than other floats, from hardware architecture viewpoint?
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11
When program will benefit from prefetch & non-temporal load/store?
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11
Inclusive or exclusive ? L1, L2 cache in Intel Core IvyBridge processor
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11
What cache invalidation algorithms are used in actual CPU caches?
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10
Linux Page Table Management and MMU
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10
Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?
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