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Pull requests list

[scudo] Lock/unlock MutexTSDs in disable/enable. compiler-rt:sanitizer compiler-rt:scudo Scudo Hardened Allocator compiler-rt
#169440 opened Nov 25, 2025 by cferris1000 Loading…
2
[TableGen] Change a reachable assert to a fatal error tablegen
#169439 opened Nov 25, 2025 by arichardson Loading…
1
[OpenMP] Preserve the original address when use_device_ptr/addr lookup fails.
#169438 opened Nov 25, 2025 by abhinavgaba • Draft
[CIR] Upstream reserved placement new handling clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#169436 opened Nov 25, 2025 by andykaylor Loading…
1
[PowerPC] Add AMO load builtins for conditional increment/decrement backend:PowerPC clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir
#169435 opened Nov 25, 2025 by maryammo Loading…
@maryammo
3
[Hexagon] Enable Machine Combiner pass. backend:Hexagon
#169434 opened Nov 25, 2025 by sgundapa Loading…
2
[CIR] Upstream non-record array init handling clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#169429 opened Nov 25, 2025 by andykaylor Loading…
1
[NFC][M68k] Refactor away MOV8dc and MOV8cd backend:m68k
#169426 opened Nov 24, 2025 by mysterymath Loading…
1
[Offloading] Extend OffloadBinary format to support multiple metadata entries
#169425 opened Nov 24, 2025 by YuriPlyakhin • Draft
2
[CIR] Only emit FP math intrinsics when precision/errno settings allow it clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#169424 opened Nov 24, 2025 by HendrikHuebner Loading…
2
[RISCV] Add a InstRW to COPY in RISCVSchedSpacemitX60.td. backend:RISC-V
#169423 opened Nov 24, 2025 by topperc Loading…
1
[LLVM] Add support for printing and parsing symbolic address spaces
#169422 opened Nov 24, 2025 by jurahul • Draft
[MLIR][XeGPU] Add two 8bit float types F8E4M3FN and F8E5M2 to valid XeGPU float type. mlir:gpu mlir
#169420 opened Nov 24, 2025 by silee2 Loading…
1
[lldb] Handle deref of register and implicit locations lldb
#169419 opened Nov 24, 2025 by dmpots Loading…
2
[CIR] Upstream var arg copy builtin clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#169415 opened Nov 24, 2025 by HendrikHuebner Loading…
2
[libc++] Remove initializer_list specific optimization in __tree
#169413 opened Nov 24, 2025 by philnik777 • Draft
[bazel] Revert 539d5d40fd42 and 223314bc04d1 bazel "Peripheral" support tier build system: utils/bazel
#169412 opened Nov 24, 2025 by googlewalt Loading…
2
[OpenACC][CIR] 'declare' lowering for globals/ns/struct-scopes (+create) clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#169409 opened Nov 24, 2025 by erichkeane Loading…
6
[lldb] [disassembler] chore: enhance VariableAnnotator to return structured data: introduce VariableAnnotator::AnnotateStructured method lldb
#169408 opened Nov 24, 2025 by n2h9 Loading…
1
[mlir][amdgpu] Add amdgpu.make_dma_descriptor
#169407 opened Nov 24, 2025 by amd-eochoalo Loading…
11
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FSUB|FMUL} backend:AMDGPU llvm:globalisel
#169406 opened Nov 24, 2025 by chinmaydd Loading…
10
[libc++] Always define _LIBCPP_GLIBC_PREREQ
#169405 opened Nov 24, 2025 by philnik777 • Draft
[CIR] CountOf VLA with Array element type clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#169404 opened Nov 24, 2025 by AmrDeveloper Loading…
1
optimize is_finite assembly backend:AArch64 backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#169402 opened Nov 24, 2025 by folkertdev Loading…
1
8
X86: make VBMI2 funnel shifts use VSHLD/VSHRD for const splats backend:X86
#169401 opened Nov 24, 2025 by ArnavM3434 Loading…
4
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