Skip to content
View JN513's full-sized avatar
🎯
Focusing
🎯
Focusing

Organizations

@LSC-Unicamp @Scarlateoficial

Block or report JN513

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
JN513/README.md

About Me

Hello, my name is Julio Nunes Avelar, a Brazilian maker since I can remember. I have a degree in Information Technology and I am currently a Computer Engineering student at the State University of Campinas (UNICAMP).

I am a huge hardware enthusiast and love developing new things. I am part of UNICAMP's study and development group for embedded systems (Embarcações). In my spare time, I maintain a technology blog called Bzóide, contribute to open-source projects, and work on some random projects, many of which are openly available on this GitHub.

Areas of Interest

  • FPGA
  • Embedded Systems
  • Computer Architecture
  • RISC-V
  • Real-Time Operating Systems (RTOS)
  • Open Source Hardware and Free Software
  • Operating Systems

Contact

My GitHub Stats:

JN513's GitHub stats


Languages I Use the Most:

Top languages used by JN513 on GitHub

Pinned Loading

  1. Risco-5 Risco-5 Public

    Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.

    Verilog 18 1

  2. Grande-Risco-5 Grande-Risco-5 Public

    Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.

    Verilog 11 1

  3. LSC-Unicamp/processor-ci-controller LSC-Unicamp/processor-ci-controller Public

    Controller module for RISC-V core CI/CD

    Tcl 17 1

  4. LSC-Unicamp/processor_ci LSC-Unicamp/processor_ci Public

    Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

    SystemVerilog 17 2

  5. Unicamp-Odhin/MFCC_Core Unicamp-Odhin/MFCC_Core Public

    MFCC Core written in SystemVerilog

    Verilog 4

  6. pico_coffee_roaster pico_coffee_roaster Public

    Raspbery Pi Pico coffe roaster project

    C 2