How to drive an externally pulled up with fpga pin?
To drive a line that has an external pull-up from an FPGA , treat the pin as open-drain/open-collector : Never drive a ‘1’. Drive ‘0’ to pull the line low. Otherwise put the pin in Hi-Z so the external resistor pulls it high. That’s it—plus a few electrical + HDL details below. HDL patterns 1) Simple open-drain output (Verilog) // pad goes low when drive_low=1, otherwise Hi-Z (external R pulls high) wire drive_low; assign PAD = drive_low ? 1'b0 : 1'bz; 2) Bidirectional, e.g., I²C SDA (Verilog) inout wire SDA; wire sda_pull_low; // 1 = pull low, 0 = release assign SDA = sda_pull_low ? 1'b0 : 1'bz; // never drive '1' wire sda_read = SDA; // read the line 3) Using vendor I/O buffers Xilinx (IOBUF): wire sda_in; wire sda_pull_low; // 1 = pull low IOBUF #(.IOSTANDARD("LVCMOS33")) iobuf_sda ( .IO(SDA), .I(1'b0), // we only ever drive 0 .O(sda_in), // readback .T(~sda_pull_low)...