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AM2432

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Dual-core Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz

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AM2432

ACTIVE
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Product details

CPU Arm Cortex-R5F Frequency (MHz) 400, 800 Certified protocol software stacks EnDat 2.2, EtherCAT, EtherNet/IP, IO-Link, Profinet Features EtherCAT, EtherNet/IP, IO-Link, Integrated industrial protocols, Profinet, TSN Operating system FreeRTOS TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution LP8733, TPS65219 Operating temperature range (°C) -40 to 125 Ethernet Yes
CPU Arm Cortex-R5F Frequency (MHz) 400, 800 Certified protocol software stacks EnDat 2.2, EtherCAT, EtherNet/IP, IO-Link, Profinet Features EtherCAT, EtherNet/IP, IO-Link, Integrated industrial protocols, Profinet, TSN Operating system FreeRTOS TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution LP8733, TPS65219 Operating temperature range (°C) -40 to 125 Ethernet Yes
FCBGA (ALV) 441 295.84 mm² 17.2 x 17.2 FCCSP (ALX) 293 121 mm² 11 x 11
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800MHz, highly-integrated for real-time processing
    • Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
    • 32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • On-Chip Debug functionality through JTAG and Trace interfaces)
  • Data Movement Subsystem (DMSS)
    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)
  • Time Sync Subsystem
    • Central Platform Time Sync (CPTS) module
    • Timer Manager (TIMERMANAGER) with 1024 timers
    • Time Sync and Compare event interrupt routers
  • 2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols
    • Backwards compatibility with 10/100Mb PRU-ICSS
    • Each PRU_ICSSG contains:
      • 3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)
        • PRU General Use core (PRU)
        • PRU Real-Time Unit core (PRU-RTU)
        • PRU Transmit core (PRU-TX)
      • Each PRU core supports the following features:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Up to 2× Ethernet ports
        • RGMII (10/100/1000)
        • MII (10/100)
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • 2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta Filter Module (SDFM) interfaces
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • 1× Enhanced Capture Module (ECAP)
      • 16550-compatible UART
        • Dedicated 192MHz clock to support 12Mbps PROFIBUS
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× Universal Asynchronous Receive/Transmit (UART) modules
  • 1× 12-bit Analog-to-Digital Converters (ADC)
    • Configurable sample rate up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (SPI) controllers
  • 3× General-Purpose I/O (GPIO) modules
  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • 2× Fast Serial Interface Transmitter (FSITX) cores
  • 6× Fast Serial Interface Receiver (FSIRX) cores

High-speed interfaces:

  • 1× Integrated Ethernet switch supporting: (CPSW)
    • Up to 2 external Ethernet ports
      • RGMII (10/100/1000)
      • RMII (10/100)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB Host, USB Device, or USB Dual-Role device
    • USB Device: High-speed (480Mbps) and Full-speed (12Mbps)
    • USB Host: SuperSpeed Gen1 (5Gbps), High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)
    • Integrated USB VBUS detection
  • 1× Serializer/Deserializer (SERDES)
    • One SERDES PHY lane to support eitherPCI-Express Gen2 or USB SuperSpeed Gen1
  • 2× Multimedia Card/Secure Digital (MMCSD) interfaces
    • One 8-bit for eMMC (MMCSD0)
    • One 4-bit for MMCSD/SDIO (MMCSD1)
    • Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-bit parallel bus with 133MHz clock or
    • 32-bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support
  • 1× Flash Subsystem (FSS) for external memory configurable as either:
    • 1× Octal SPI (OSPI) flash interface
    • or 1× Quad SPI (QSPI) flash interface
  • Simplified power sequencing requirements
  • Dual-voltage I/O Support (3.3V / 1.8V)
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for monitoring over-voltage and under-voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with dedicated error pin
    • ECC and parity on select internal bus interconnects
    • Run-time safety diagnostics, including:
      • Voltage, Temperature, and Clock Monitoring
      • Windowed Watchdog Timers
      • CRC Engine for memory integrity checks
    • MCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Controlled reset isolation
      • Dedicated MCU PLL and MMR control
      • Separate I/O voltage supply rail
  • Supports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.
  • 16-nm FinFET technology
  • ALV: 17.2mm × 17.2mm, 0.8mm pitch(441-pin) [Lidded] Flip-Chip Ball Grid Array(FCBGA)
  • ALX: 11.0mm × 11.0mm, 0.5mm pitch(293-pin) [Overmolded] Flip-Chip Chip Scale Package(FCCSP) 
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800MHz, highly-integrated for real-time processing
    • Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
    • 32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • On-Chip Debug functionality through JTAG and Trace interfaces)
  • Data Movement Subsystem (DMSS)
    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)
  • Time Sync Subsystem
    • Central Platform Time Sync (CPTS) module
    • Timer Manager (TIMERMANAGER) with 1024 timers
    • Time Sync and Compare event interrupt routers
  • 2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols
    • Backwards compatibility with 10/100Mb PRU-ICSS
    • Each PRU_ICSSG contains:
      • 3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)
        • PRU General Use core (PRU)
        • PRU Real-Time Unit core (PRU-RTU)
        • PRU Transmit core (PRU-TX)
      • Each PRU core supports the following features:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Up to 2× Ethernet ports
        • RGMII (10/100/1000)
        • MII (10/100)
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • 2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta Filter Module (SDFM) interfaces
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • 1× Enhanced Capture Module (ECAP)
      • 16550-compatible UART
        • Dedicated 192MHz clock to support 12Mbps PROFIBUS
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× Universal Asynchronous Receive/Transmit (UART) modules
  • 1× 12-bit Analog-to-Digital Converters (ADC)
    • Configurable sample rate up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (SPI) controllers
  • 3× General-Purpose I/O (GPIO) modules
  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • 2× Fast Serial Interface Transmitter (FSITX) cores
  • 6× Fast Serial Interface Receiver (FSIRX) cores

High-speed interfaces:

  • 1× Integrated Ethernet switch supporting: (CPSW)
    • Up to 2 external Ethernet ports
      • RGMII (10/100/1000)
      • RMII (10/100)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB Host, USB Device, or USB Dual-Role device
    • USB Device: High-speed (480Mbps) and Full-speed (12Mbps)
    • USB Host: SuperSpeed Gen1 (5Gbps), High-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps)
    • Integrated USB VBUS detection
  • 1× Serializer/Deserializer (SERDES)
    • One SERDES PHY lane to support eitherPCI-Express Gen2 or USB SuperSpeed Gen1
  • 2× Multimedia Card/Secure Digital (MMCSD) interfaces
    • One 8-bit for eMMC (MMCSD0)
    • One 4-bit for MMCSD/SDIO (MMCSD1)
    • Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-bit parallel bus with 133MHz clock or
    • 32-bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support
  • 1× Flash Subsystem (FSS) for external memory configurable as either:
    • 1× Octal SPI (OSPI) flash interface
    • or 1× Quad SPI (QSPI) flash interface
  • Simplified power sequencing requirements
  • Dual-voltage I/O Support (3.3V / 1.8V)
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for monitoring over-voltage and under-voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with dedicated error pin
    • ECC and parity on select internal bus interconnects
    • Run-time safety diagnostics, including:
      • Voltage, Temperature, and Clock Monitoring
      • Windowed Watchdog Timers
      • CRC Engine for memory integrity checks
    • MCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Controlled reset isolation
      • Dedicated MCU PLL and MMR control
      • Separate I/O voltage supply rail
  • Supports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.
  • 16-nm FinFET technology
  • ALV: 17.2mm × 17.2mm, 0.8mm pitch(441-pin) [Lidded] Flip-Chip Ball Grid Array(FCBGA)
  • ALX: 11.0mm × 11.0mm, 0.5mm pitch(293-pin) [Overmolded] Flip-Chip Chip Scale Package(FCCSP) 

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.

The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.

The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.

The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.

The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.
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AM2431 ACTIVE Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz Single-core variant of AM243x family of ARM® Cortex-R5F based microcontrollers
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet AM243x Sitara™ Microcontrollers datasheet (Rev. H) PDF | HTML 19 Dec 2025
* Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0 (Rev. J) PDF | HTML 13 Nov 2025
* User guide AM64x/AM243x Technical Reference Manual (Rev. J) 08 May 2026
Application note Enhanced OSPI PHY Tuning Algorithm for Sitara Processors on MCU+ SDK PDF | HTML 13 Mar 2026
Application note Throughput Characterization of OSPI and QSPI Serial NOR/NAND Flash Operations PDF | HTML 17 Feb 2026
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 12 Feb 2026
Application note Getting Started with Sysconfig Tool PDF | HTML 21 Nov 2025
User guide Hardware Design Considerations for Custom Board Using AM6442, AM6422, AM6412 and AM2434 (ALV, ALX) Processor (Rev. D) PDF | HTML 24 Oct 2025
User guide AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist (Rev. E) PDF | HTML 10 Oct 2025
Application note Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 03 Sep 2025
Functional safety information AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 17 Jul 2025
Application note Processors Tools Overview PDF | HTML 16 Jun 2025
White paper Functional Safety Support for Arm®-based Microcontrollers and Processors (Rev. A) PDF | HTML 10 May 2024
Functional safety information AM64x, AM243x IEC61508 TUV SUD Functional Safety Certificate 25 Mar 2024
Product overview AM243x OSPI, QSPI Flash Selection Guide (Rev. A) PDF | HTML 06 Feb 2024
Product overview Industrial Communication Protocol Support for Arm®-based Microcontrollers and Processors PDF | HTML 22 Dec 2023
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
Product overview Functional Safety for AM2x and Hercules™ Microcontrollers PDF | HTML 08 Nov 2023
Application note Sitara MCU Thermal Design PDF | HTML 11 Sep 2023
Application brief EtherCAT Connected Motor Drive System With Endat 2.2 Absolute Encoder Feedback PDF | HTML 07 Sep 2023
Application note Integration of MbedTLS on SITARA MCU Devices PDF | HTML 03 Aug 2023
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 31 Jul 2023
User guide 10-kW, Three-Phase, Three-Level (T-Type) Inverter Using AM263 PDF | HTML 11 Jul 2023
Certificate BP-AM2BLDCSERVO EU Declaration of Conformity (DoC) 28 Jun 2023
Application note Powering the AM243x With the TPS65219 PMIC PDF | HTML 26 Jun 2023
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24 May 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Application note FSI Bandwidth-Optimization for Multi-axis Servo Control PDF | HTML 14 Dec 2022
Application note Debugging Sitara AM2x Microcontrollers PDF | HTML 24 Oct 2022
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 11 Oct 2022
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 08 Aug 2022
Application note AM64x/AM243x Extended Power-On Hours PDF | HTML 05 Aug 2022
Application note AM243x/AM64x Single Chip Motor Control Benchmark PDF | HTML 30 Mar 2022
Application note Using LP8733xx and TPS65218xx PMICs to Power AM64x and AM243x Sitara Processors PDF | HTML 16 Feb 2022
White paper Industry 4.0 서보 드라이브에 Sitara™ 프로세서 및 마이크로컨트롤러 활용 (Rev. C) PDF | HTML 12 Jan 2022
White paper 運用適合工業 4.0 Sitara™ 伺服驅動器的處理器與微控制器 (Rev. C) PDF | HTML 12 Jan 2022
White paper Utilizing Sitara Processors and Microcontrollers for Industry 4.0 Servo Drives (Rev. C) 06 Oct 2021
White paper Revolutionizing Real-Time Control, Networking and Analytics w/ Sitara™ AM2x MCUs PDF | HTML 07 Jul 2021
Application note AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) PDF | HTML 01 Jul 2021
Application note AM64x/AM243x Power Estimation Tool (Rev. A) PDF | HTML 01 Jul 2021
More literature LaunchPad™ kit with Sitara™ AM243x MCU Pinout Map 18 Jun 2021
White paper Sitara™ AM2x MCU를 통한 실시간 제어, 네트워킹 및 분석 성능 혁신 13 Jun 2021
White paper 以 Sitara™ AM2x MCU 顛覆即時控制、網路與分析效能 13 Jun 2021
User guide AM64x/AM243x BGA Escape Routing (Rev. A) PDF | HTML 06 Apr 2021
Functional safety information The state of functional safety in Industry 4.0 27 Nov 2018

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