I am trying to understand interrupts at both the hardware and OS level.
Why exactly we need an APIC controller in a system. I understood that it is doing some multiplexing and only one line is going to CPU. If we have enough lines in the processor to be utilized by external hardware for interrupts, Can we do that?
What happens when we return ISR without IRQ_HANDLED?
How we can find out why our ISR is not handled even if we got interrupt(Consider that we have registered and initialized ISR).
In StackExchange, you should post each question as a separate question post. Also, your questions 2 and 3 are mostly kernel programming questions, and so they might better fit Stack Overflow instead. I'd recommend that you edit this question to only contain your question 1 and post the other questions separately, perhaps to Stack Overflow.
Regarding your question 1:
Sure you could do that... but then you would be designing a new hardware architecture that would no longer be PC-compatible.
The APIC is an enhanced replacement of the old 8259A Programmable Interrupt Controller (PIC) chip of the original PCs.
The PIC was designed for the 8085 and 8086 microprocessors, to expand their limited interrupt capabilities. It was adequate for the old ISA bus, but with more modern bus types, it became a bottleneck for system performance and expandability. In particular, the PIC was inadequate for constructing multi-processor systems.
So, the Advanced Programmable Interrupt Controller (APIC) architecture was designed as a replacement. The first APIC was a discrete chip, 82489DX. It enabled the construction of the first dual-CPU systems in the 486 and early Pentium era. Since then, the "local APIC" functionality has been integrated into the CPU itself.
APIC can emulate the old PIC at the hardware level if/when required, but can work in more advanced modes with modern operating systems.
