I am trying to automate some make commands. Along with the target we have a variable that is passed to make (corresponding to set of a #ifdef's in code).
The make command looks like this:
make <target> <MYCDEF=val>
val can take multiple values (MYCDEF_VAL1, MYCDEF_VAL2...).
target can also take multiple values like: android_arm, windows_x86, linux_x64 etc.
The MYCDEF_VALn can be found from a config.h where we check for
#elif (defined MYCDEF_VALn)
So, I can get all MYCDEF values using gawk -f script1 config.h
script1:
{
if(/defined.*MYCDEF_/)
{
k=index($0, "MYCDEF_");
print substr($0, k, index($0, ")")-k) #all lines of type defined(MYC_DEF_VALn)
}
}
To get all targets, I can read Makefile using gawk -F: -f script2 Makefile
script2:
{if(/^[A-Za-z0-9_]+:$/) print $1}
To build for all MYCDEF_ vals with one target I can pipe the output from first script (using config.h):
gawk -f script1 config.h | xargs -I {} -n 1 make -kj windows_x86 MYCDEF={}
Similarly for all targets with one MYCDEF_val, I can pipe from second script (using Makefile).
gawk -f script2 Makefile| xargs -I {} -n 1 make -kj {} MYCDEF=MYCDEF_VAL1
Now, we want to build with all values of MYCDEF_ for all targets. It can be done using for loop:
for i in $(gawk -f script2 Makefile)
do
gawk -f script1 config.h | xargs -I {} -n 1 make -kj $i MYCDEF={}
done
Is there a oneliner for this?