LLVM code generator: is Machine code representation machine-agnostic?

Question

Please note: this question is not about LLVM IR, but LLVM's MIR, an internal intermediate representation lower than the former one.

This documentation on LLVM Machine code description classes, says (highlighting mine):

At the high-level, LLVM code is translated to a machine specific representation formed out of MachineFunction , MachineBasicBlock , and MachineInstr instances...

However, the same paragraph goes on and says:

This representation is completely target agnostic, representing instructions in their most abstract form...

My question is, how to understand this paragraph?

I have a hard time reconciling the claim that this intermediate representation is machine specific and target agnostic at the same time. I thought "machine" and "target", in LLVM's context, mean the same thing - the instruction set architecture (e.g. x86_64, MIPS) used by the compiled executable.

Examples are welcome.

arnt · Accepted Answer · 2018-09-30 19:32:19Z

1

There are different ways to be platform specific. For instance, you could have a differently-named opcode for add, or perhaps with different overflow semantics, or you could use the same add for all, with the operands/flags specified by the same arguments for all target platforms, with the same default values.

And there are many target-specific details such as the size or alignment of pointers that affect your code even if they don't affect any single instruction.

Machine IR represents instructions in their most abstract form. It doesn't try hide that on this target, pointers have 32 bits.

answered Sep 30, 2018 at 19:32

arnt

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2 Comments

Leedehai Over a year ago

Thanks. If the instruction set is given, e.g. x86, are there any rooms for the ambiguities you mentioned above?

arnt Over a year ago

If I understand the comment correctly, then I'm not sure but MIR is SSA and x86 wasn't designed for SSA, so there's at least a risk of ambiguity. If I don't, then I don't understand. Sorry.

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