Understanding Some Makefile Syntax

Question

I saw a Makefile that looks like:

TESTTMP = ./test-tmp

# VANILLA REDIS CONF
define VANILLA_CONF
daemonize yes
port 6379
dir .
pidfile redis_vanilla.pid
logfile redis_vanilla.log
save ""
appendonly no
endef

export VANILLA_CONF

.ONESHELL:   # what's it used for?
start: cleanup
    mkdir -p $(TESTTMP)
    cd $(TESTTMP)
    echo "$$VANILLA_CONF" | redis-server -  # what does this look like when expanded, equivalent to what command?

cleanup:
    rm -rf $(TESTTMP)

stop:
    kill `cat $(TESTTMP)/redis_vanilla.pid` || true  # what's "|| true"
    make cleanup

Basically I need to modify it for my own use, but there're some lines that I don't quite understand. I've made the comments in the code. Any help would be appreciated. Thanks.

Answer 1

If you want to see the output of echo $$VANILLA_CONF, then simply remove the | redis-server -, and the output will be displayed on your screen.

In this line, the $ is doubled as a means of ‘escaping’ it in the Makefile: Make expands the echo $$VANILLA_CONF to echo $VANILLA_CONF, and passes that to the shell, which expands the shell variable VANILLA_CONF (a common error in this context is to forget to double the $ sign: if the line were instead echo $VANILLA_CONF, then Make would attempt to expand the makefile variable V, which, being undefined, would expand to nothing, and the shell would receive the perplexing string echo ANILLA_CONF.

The | redis-server - is just standard shell syntax, indicating a pipeline: the text echoed into the pipe by the echo command is read from its standard input by the program redis-server (whatever that is).

The || shell connector means ‘or’: if (and only if) the command before the || fails, then the command after it is executed. In this case, the command after the || is true, which always succeeds. That is, this line in the stop rule will succeed even if the kill fails (there are other ways to express this in Makefile syntax, but I think this is clearer). This is also standard shell syntax.

This may seem slightly confusing, because you have to be able to identify what is make syntax and what is shell syntax. The basic idea with ‘make’ is that it sends each of the ‘rule’ lines to a shell process, after expanding make variables with $(varname) (or $x for (rare) single-letter variable x and various escapes such as $$ for $, as above). You might want to review the documentation for ‘make’ (the wikipedia page seems to have enough detail to cover what you need, but it links to the more extensive manual, if that's necessary).