New answers tagged fpga
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On ECP5, which power pins are utilized by differential pairs?
While the text does not explicitly state that the differential drivers are powered by VCCIO, I've since noticed that the figure 4.3 does show VCCIO as the power input to the differential driver.
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How to interface ADA4355 ADC with Spartan-6 SLX9 FPGA (16-bit DDR/SDR modes)?
On Spartan-6, you can’t deserialize more than 8 bits per pin, so the practical way to capture the ADA4355’s 16-bit DDR output is to use the “two-lane, 1× frame, DDR” mode — not the single-lane 16-bit ...
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Decoupling/bypass strategy for EPC5 FPGA BGA with only top layer assembly?
Some recommend a certain number of capacitors "per [power] pin" but I've always been hazy on what the justification is for that rule.
I'd call that a requirement, not a recommendation. ...
- 110k
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Accepted
What could be wrong with my vivado simulation? The clock isn't alternating
It appears your view is zoomed in too much. The timestamps on waveforms show 1ps distance between marks, while your clock should have transitions every 5ns, i.e. 5000 times slower. You should zoom out....
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Push-pull along with pull-up
You are misinterpreting the specs.
Any digital IO defines the output high voltage when it outputs some defined current into a load, so voltage will be lower than VCC.
A pull-up to same VCC does not ...
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