Questions tagged [rgmii]
Reduced Gigabit Media Independent Interface (RGMII) is a parallel interface from MAC to external PHY that uses DDR I/O to reduce the pin count.
20 questions
1
vote
1
answer
70
views
What is the maximum inter-lane skew length for RGMII 1000 Mbit/s?
What is the maximum inter-lane skew length for RGMII 1000 Mbit/s?
I'm looking at ST Microelectronics' Hardware Guidelines AN5489 for STM32MP SoC. It says that traces should be short with 'balanced ...
- 1,466
-1
votes
1
answer
555
views
How to define PHY mode and MAC mode between back to back switches
I'm planning to use this Switch IC connected to another another switch ic which is the same part number. When connecting these devices in back to back mode with RGMII interface between then, I need to ...
- 1,737
1
vote
2
answers
1k
views
RGMII use RX CLK as TX CLK
I'm looking into the RGMII interface spec and something is unclear to me. The PHY gives my FPGA a 125 MHz clock in 1 GBit mode. I also have to send out a TX clock at 125 MHz. Is it legal to use the RX ...
0
votes
0
answers
283
views
Connecting two ethernet ports back to back
Suppose, I am connecting the copper ports of 2 PHYs in back-to-back mode in the same board (using capacitive coupling technique), should the TX pair of one PHY be connected to the Rx pair of the other ...
user220456
0
votes
2
answers
3k
views
How to use Gigabit Ethernet with MCU?
I am new at ethernet and it comes complex. Trying to use STM32's RMII interface with switch. I just want to see at IT's switch gigabit port. I don't want to transfer data gigabit, it doesn't matter. ...
1
vote
1
answer
4k
views
Ethernet with STM32
I designed an ethernet microchip with reference (LAN8742A-LAN8742) with MCU STM32F767ZGT6, so I followed some document routing ethernet in PCB I respect all rules. when I put the ethernet there is a ...
- 176
0
votes
1
answer
281
views
Will RGMII work with a small constant delay in the range of 10~20ns on all signals?
Related to this question.
An RGMII interface transmitting data at 1Gbps runs with a clock rate of 125MHz, and data is clocked out on both edges. Given that, it would appear that any skew between ...
- 13.5k
0
votes
0
answers
322
views
Smallest lowest cost way to isolate RGMII signals between devices on the same CCA?
I have a single Gigabit Ethernet line coming out of a circuit card. Access to the line will be shared by two CPUs. To facilitate shared access, the CCA will have an Ethernet switch IC.
The switch IC ...
- 13.5k
0
votes
0
answers
419
views
Can you interface 2 gigabit ethernet ports via one rgmii interface?
Can we use the KSZ9893RNXC from Microchip as the Ethernet PHY chip, and interface the 2 gigabit ports to Allwinner H6, which has only one RGMII interface. Also please note that we are aiming at using ...
4
votes
2
answers
6k
views
Impedance/Termination of Marvell PHY
I'm trying to understand the proper way to design a PCB to interface a Xilinx 7-series FPGA with a Marvell 88E1512 Ethernet PHY, without simply copying the design from an existing schematic.
The ...
- 755
1
vote
1
answer
240
views
Ethernet Phy Rx developed in a FPGA to send data to an ethernet Mac
I'm trying to send data from a FPGA to the Ethernet Mac port of a SoC which has the stmmac Synopsys IP.
I'm using the MII protocol at 25MHz for 100Mb/s (4-bit per clock cycle).
I'm sending the ...
- 701
0
votes
0
answers
294
views
Can I use an Ethernet switch IC without connecting to the mcu?
I'd like to add an unmanaged Ethernet switch IC to a board I am designing, but I have no free RGMII/SGMII/PCIe connection available on my MCU. The goal of this IC is just to save space/hassle (in the ...
- 25
0
votes
2
answers
574
views
IO standard for RGMII interface of ethernet
I'm learning about the RGMII interface of ethernet. Can anybody please tell me What IO standard does the TX and RX line of RGMII interface support? Please help. I'm just a beginner
- 29
1
vote
1
answer
1k
views
How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?
The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics ...
- 41
2
votes
1
answer
314
views
NIC connection with PHY issue
We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected ...
- 21