Input on MDI Ethernet trace design

Question

I am working on a 4-layer PCB board at the moment and trying to integrate 10/100 ethernet. I just wanted some input on the differential pair routing. I have a general idea of what I'm doing and have done similar in the past with USB. I've only designed 2-layer boards before, but went with 4 this time as it wasn't feasible to have these MDI lines on 2 layers...

Here is a screenshot of my current routing. I have a conductor width of 0.24 mm, spacing of 0.3048 mm, distance to the ground plane of 0.2104 mm and relative permittivity of 4.4. Based on my calculations this should be 99.736 Ohms differential, which is well within tolerance. The total trace length is ~24mm. Does my length tuning look fine in this design, could this cause any issues?

I have read TI's guide for ethernet lines, but I'm still worried. They mention the single ended impedance should be 50 Ohms +/- 10%. If I am interpreting this correctly, that would be the impedance of one line to ground? When I run that through a calculator, I am off. Are you supposed to manipulate values to find a middle ground to get close to ideal z diff and z single? Sorry if this is a stupid question, just looking for clarification.

Overall, I just want to make sure I am not missing anything extremely important, I'd rather not waste a print.

In case it helps, I am doing this with a WIZ5500 ethernet chip and an integrated magnetics ethernet connector.

Answer 1

Your starting point is correct. It is generally not feasible to use 2-layer boards for anything that requires impedance control, so 4 layers is a good starting point.

Based on your calculations the differential impedance does match 100 ohms so I won't double check them. Not all application notes say which single-ended impedance should be used, and even those that do don't necessarily agree on single value, because like always, it depends on what you want to optimize for. Not all appnotes agree on the 100 ohm differential impedance on PCB either, for reasons what should be optimized.

Generally the 50 ohm single ended impedance is a good starting point as well.

E.g. Sierra Circuits suggest 95 ohms differential for the MDI traces and 55 ohm single ended.

Many sources say different values for intra-pair length matching as well, but 50 mils should be good for 100M Ethernet, which you have succeeded fine.

You as have no vias and have minimized the trace length to below an inch, which is good. Many sources say it should not exceed 1 or 2 inches.

The only improvements you can make arw the following.

The 50 ohm termination resistors should be as close to the PHY chip pins as possible. Some sources say within 400 mils or 10mm. They are approximately 10mm away so they could be closer.

Another thing are the pads of the resistors. The pad is a square which is wider than impedance controlled PCB track and has some length. Which means it has lower impedance than PCB track and since there is ground plane under it, it can be thought as a small capacitor. In order to reduce the effect of the resistor pad, in high speed designs the ground plane has a pad-shaped void under the pad, usually on ground plane only, not on all planes under the pad.

In context, 100Base-TX has signal rise/fall times that are as sharp as 3ns, which means travel distance about 59cm, and by using the 10x rule of thumb, if the 100Base-TX signal traces are less than 5.9cm don't necessarily need to be considered as transmission lines. For 12 Mbps USB, that critical trace length is about 15cm, and for 480 Mbps USB, less than 1cm.