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After releasing a firmware update for my custom device, I started noticing that some units were failing to operate correctly. I discovered that writing to the flash memory while the system voltage is below a safe threshold that mentioned in datasheet can lead memory corruption. So every time the software attempted to read from the corrupted flash region, it would consistently trigger an NMI (Non-Maskable Interrupt) due to ECC (Error-Correcting Code) faults.

To protect, I implemented a safeguard in the firmware: if an ECC error is detected during runtime, the system will automatically erase the affected flash region to prevent repeated NMI handler interrupt and restore stability.

This incident led me to a broader question: aside from NMI and HardFault, are there any other exception or fault handlers available on STM32 devices that could be useful in similar scenarios?

I heard there are some errors (MPU Fault Handler, Bus Fault Handler, UsageFault_Handler). Will they also trigger NMI?

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  • \$\begingroup\$ Which STM32 is this? Please provide exact part number you are using, so we can open the same datasheets and reference manuals. \$\endgroup\$ Commented Apr 4 at 10:22
  • \$\begingroup\$ Yes. sorry i want to ask general question. I am using SMT32G0B1RE. \$\endgroup\$ Commented Apr 4 at 11:18

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The list of interrupt vectors is specific to a MCU series or family and each has different features.

For example if you are using the STM32G0B1RE MCU, the Reference Manual os shared between all G0x1xx chips.

The NMI on this chip is one specific vector that triggers on many things. Other vectors may be useful to you.

It might be best to enable power voltage monitor inside the chip or add an external supply voltage monitor chip that keeps the MCU reset while there is insufficient supply voltage.

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Based on RM0454, specifically Table 45 on page 250, it appears that the primary interrupts responsible for error handling in STM32 are the NMI and HardFault handlers. So, it would be more effective to focus on monitoring whether the system ends up in either of these two handlers, regardless of what reason. At the end of the day, what matters most is being able to detect and recover from these critical events. enter image description here

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