We are using output of deserializer MAX9280 for display. The resolution is 800x480 with frame rate of 60hz. PCLK is around 25Mhz. We thought length matching is not important in this application, so did not bother doing that. However, the image is abnormal. I measured the trace length. The shortest being PCLK is 22mm, and one of the data line being longest at 62mm. Per this discussion, do I just need to make the PCLK the longest, or the length of all traces should be better matched?
attached are pictures of abnormal and normal displayed images.
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3\$\begingroup\$ What exactly are we looking at in the second picture? \$\endgroup\$Dave Tweed– Dave Tweed2025-03-05 01:33:15 +00:00Commented Mar 5 at 1:33
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\$\begingroup\$ we'll need some kind of schematic that incorporate the two large ICs and what you put between them; also, really, hard to assess what goes wrong without at least one or two eye diagrams measured on both sides of these 8-contact ICs between them. \$\endgroup\$Marcus Müller– Marcus Müller2025-03-05 10:57:57 +00:00Commented Mar 5 at 10:57
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We can't know how "open" your eye diagram is, i.e., how much skew you can actually deal with. However, travelling 40 mm would take a signal in a cable or on a PCB around 0.2 nanoseconds, and at 25 MHz, one symbol takes 40 nanoseconds. So, your clock skew is < 2%. That probably won't be the problem. So, better length matching won't solve the problem you're having.
It's much more likely you introduced a severe signal integrity problem, and the receiver hence can't correctly synchronize anymore. You will have to show the trace and reference (==ground) design, and show that you did make sure you're correctly terminating, that for the sharpness of edges your receiver needs, you've designed the traces with high enough bandwidth, and that you, overall, applied sane signal design. I suspect, unless your design is surprisingly bad, without a test pattern and an appropriate oscilloscope, this will be hard to debug.
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\$\begingroup\$ I have added a picture of trace routing in the OP. The top and bottom layer traces between the two IC's are the parallel signals. the green traces are CAN and LIN signals on inner layer 1. Probly should move those away? The board is still at my colleague's lab and I won't be able to measure the signal until a few days later. \$\endgroup\$WX369– WX3692025-03-05 08:32:09 +00:00Commented Mar 5 at 8:32
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\$\begingroup\$ I presume there's a power plane and a ground plane, separated from the signal layers via some rather thin PCB substrate? \$\endgroup\$Marcus Müller– Marcus Müller2025-03-05 10:21:10 +00:00Commented Mar 5 at 10:21
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\$\begingroup\$ Yes. Four layer PCB. Inner layer one is power plane and Inner layer two is ground plane. Added the relevant schematic for reference in OP. The test pattern output from LT9211C is normal, so the issue is from the input side. \$\endgroup\$WX369– WX3692025-03-05 16:59:30 +00:00Commented Mar 5 at 16:59