jtag boundary scan pin testing

Question

I'm finding some JTAG documentation a bit lacking in examples of what I call "typical sequences." My goal is to wiggle a GPIO pin of my device using the JTAG interface. Using the BSDL file for my specific device, I have identified the correct CELL index in the boundary scan register for my pin-of-interest's output3 cell (let's call it index j), I have identified the "output disable" control CELL index for the same pin-of-interest (let's call this index k), and I have identified the "disable" bit polarity required to enable/disable the GPIO output driver (assume a logic '1' puts the pin into high impedance). I have identified the total length of the BOUNDARY_REGISTER (let's call it length N), and identified every single "safe" default bit polarities for every single CELL (let's assume all safe values are a logic '1').

Question Number 1: To drive the output high, would this be the basic sequence of JTAG flow? Step 1) Send the "SAMPLE/PRELOAD" command to the Instruction Register (IR) ("sending" implies walking through all the JTAG TAP controller states and ending back at the RUN/IDLE state). Step 2) Shift N bits to the Data Register (DR), with all bits being the "safe" logic-1 except bit number k, since a low in this bit will enable the output for the pin. Step 3) Send the "EXTEST" command to the Instruction Register (IR), the output pin will update upon completing the Update-IR state. To then change the output to a low state, I would repeat steps 1, 2, and 3, except I will now also set bit number j low in the DR as this sets the output low.

Question Number 2: When sending the N bits to the DR, is it sent LSb first (cell index 0 is sent first), or MSb first (cell index N-1 is sent first)? Or is this manufacturer specific?

Answer 1

You're correct, and this is LSB first.

TL;DR

• You shift IR Sample/Preload, then shift DR to N bits of boundary scan register. This initializes the future pin state.
• As soon as you set IR to Extest (go through Update-IR, actually), pins will be controlled by boundary scan register values (output value, tri-states), values you've set at previous step.
• As long as IR stays Extest, you can go through Capture-DR, Shift-DR and Update-DR as many times as needed (without touching IR at all). Each time you go through Capture-DR, boundary cell state will be copied to boundary scan register, ready to be shifted out, each time you go through Update-DR, boundary scan register will be committed to boundary cells (i.e. pins). All you have to do is issue a N-bit DR shift between Capture-DR and Update-DR to simultaneously extract current pin state, and inject future pin state.
• When you're done with Extest, set IR back to Bypass (for instance), and pin control will be back as normal.

Actually, Sample/Preload and Extest have the exact same effect on the the boundary scan and boundary cell behavior. The only difference between the two is when IR is Extest, pin control is from boundary cells, not from internal logic.

In JTAG, all registers are shifted in (and out) LSB first.