I am using 3 Artix-7 FPGAs in my design. Is it possible to use single SPI configuration Flash to program 3 FPGA device.
I have found information about multiple boots for one FPGA but not multiple FPGA booting using one boot memory.
2
-
\$\begingroup\$ there are multiplexers that can switch multiple lines in parallel and attach them to different FPGA at a time. And you can control that mux with a small microcontroller or from the first FPGA. Does this idea make any sense? \$\endgroup\$Ilya– Ilya2020-12-09 12:53:07 +00:00Commented Dec 9, 2020 at 12:53
-
\$\begingroup\$ First check manufacturer app notes. If not, everyone long since lets you read the rest of the chip so have the first FPGA push configuration to the others. But SPI flashes cost nothing compared to FPGAs and this scheme may lose you some flexibility in working with what sounds to be a quite expensive board. So maybe it's actually as unwise as it seems clever. \$\endgroup\$Chris Stratton– Chris Stratton2020-12-09 15:34:08 +00:00Commented Dec 9, 2020 at 15:34
Add a comment
|
2 Answers
\$\begingroup\$
\$\endgroup\$
I did this (booting 27 FPGAs) using spi slave boot mode. One FPGA or MCU serves as master and the others slaves. No problem. See chapter "Slave Serial Configuration" UG470.
\$\begingroup\$
\$\endgroup\$
Bit-stream loading for the Artix-7 is described in detail in Xilinx UG470.
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
Specifically chapter 9 addresses configuration of multiple FPGAs.
Multiple FPGAs can be configured in slave serial mode from a small micro-controller as shown.
You might also consider configuring the first FPGA in master serial mode, and then using the first FPGA to configure the next ones in slave serial mode. Its possible to store all three bit-streams in a single SPI flash. The SPI interface on the FPGA becomes user IO after configuration so the first FPGA can read the other bit-streams from the flash. You will need to use the STARTUPE2 Primitive to access the SPI flash clock.
