Cisco seriously amps-up Silicon One chip, router for AI data center connectivity

Cisco has unwrapped a high-end, 51.2 Tbps router and chip that it says will go a long way toward supporting the distributed AI workloads of today and in the future.

Aimed at hyperscalers and large data center operators, the Cisco 8223 routing system is based on a new iteration of the company’s Silicon One portfolio: the P200 programmable, deep buffer chip. The system supports Octal Small Form-Factor Pluggable (OSFP) and Quad Small Form-Factor Pluggable Double Density (QSFP-DD) optical form factors that help the box support geographically dispersed AI clusters.

“Power constraints and resiliency requirements are causing hyperscalers, neoclouds, and enterprises to embrace distributed AI clusters that span campus and metro regions, all of which need secure, high-performing, high-capacity, and energy-efficient connectivity,” wrote Rakesh Chopra, Cisco Fellow and senior vice president for Silicon One, in a blog post about the new system. “The Cisco 8223 is optimized for large-scale disaggregated fabrics within and across data centers, enabling customers to scale AI infrastructure with unmatched efficiency and control.”

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Cisco Silicon One processors are purpose-built to support high network bandwidth and performance and can be customized for routing or switching from a single chipset, eliminating the need for different silicon architectures for each network function. Core to the Silicon One system is its support for enhanced Ethernet features, such as improved flow control and congestion awareness and avoidance.

A single P200-based system handles the traffic that previously required six 25.6 Tbps fixed systems or a four-slot modular system, Chopra said. In addition, the 8223 3RU, 51.2 Tbps configuration consumes about 65% less power than prior generations, he stated.

The 8223 features 64 ports of 800G coherent optics support and is capable of processing over 20 billion packets per second, according to Chopra. It features advanced buffering at its core to handle the massive traffic surges from AI training application traffic. The P200 enables the router to support full 512 radix, and it can scale to 13 petabits using a two-layer topology, or up to a massive 3 exabits using a three-layer topology, Chopra added.

Some say deep buffers shouldn’t be used to handle this type of traffic; the contention is that these buffers fill and drain, creating jitter in the workloads, and that slows things down, Chopra told Network World. “But the real source of that challenge is not the buffers. It’s a poor congestion management scheme and poor load balancing with AI workloads, which are completely deterministic and predictable. You can actually proactively figure out how to place flows across the network and avoid the congestion,” he said.

The 8223’s deep-buffer design provides ample memory to temporarily store packets during congestion or traffic bursts, an essential feature for AI networks where inter-GPU communication can create unpredictable, high-volume data flows, according to Gurudatt Shenoy, vice president of Cisco Provider Connectivity. “Combined with its high-radix architecture, the 8223 allows more devices to connect directly, reducing latency, saving rack space, and further lowering power consumption. The result is a flatter, more efficient network topology supporting high-bandwidth, low-latency communication that is critical for AI workloads,” Shenoy wrote in a blog post.

NOS options

Notably, the first operating systems that the 8223 supports are the Linux Foundation’s Software for Open Networking in the Cloud (SONiC) and Facebook open switching system (FBOSS) – not Cisco’s own IOS XR.  IXR will be supported, too, but at a later date, according to Cisco. 

SONiC decouples network software from the underlying hardware and lets it run on hundreds of switches and ASICs from multiple vendors while supporting a full suite of network features such as Border Gateway Protocol (BGP), remote direct memory access (RDMA), QoS, and Ethernet/IP. One of the keys to SONiC is its switch-abstraction interface, which defines an API to provide a vendor-independent way of controlling forwarding elements such as a switching ASIC, an NPU, or a software switch in a uniform manner.

SONiC is seen as a significant alternative to more traditional, less flexible network operating systems. Its modularity, programmability and general cloud-based architecture could make it a viable option for enterprises and hyperscalers to deploy as cloud networking grows.

“If you look at who needs this kind of capacity now, the first use case is the hyperscalers, and the 8000 series is what we sell into our hyperscaler customers,” Chopra said.  “As larger enterprises and other move toward AI, the other operating system support will follow.”

Silicon One portfolio expands

The 8223 is the latest in a series of switch/router upgrades Cisco has made to its Silicon One family. 

In June, Cisco added two new programable Silicon One-based Smart Switches: the C9350 Fixed Access Smart Switches and C9610 Modular Core. Both are built for AI workloads, such as agentic AI, generative AI, automation and AR/VR. Earlier this year Cisco unwrapped a family of data center switches based on the Silicon One chip that includes built-in programmable data processing units (DPU) from AMD to offload complex data processing work and free up the switches for AI and large workload processing.

Cisco now has 14 varieties of Silicon One ASICs running the gamut from leaf/top-of-rack campus switching to high-throughput AI-backbone applications. The silicon is a key part of a variety of core switches and router in Cisco’s networking portfolio, from the Nexus Series 8000 for telco/hyperscaler environments to the Catalyst 9500X/9600X enterprise campus switches and 8100 line of branch and edge devices.    

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