YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Trending
See what the GitHub community is most excited about today.
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
corundum / corundum
Open source FPGA-based NIC and platform for in-network compute
EttusResearch / uhd
The USRP™ Hardware Driver Repository
google / CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
Xilinx / libsystemctlm-soc
SystemC/TLM-2.0 Co-simulation framework
RapidSilicon / litex_reference_designs
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
chipsalliance / yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
pConst / basic_verilog
Must-have verilog systemverilog modules
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
efabless / caravel_user_project
analogdevicesinc / hdl
HDL libraries and projects
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
zeroasiccorp / umi
Universal Memory Interface (UMI)
chipsalliance / synlig
SystemVerilog support for Yosys
nvdla / hw
RTL, Cmodel, and testbench for NVDLA
