The Wayback Machine - https://web.archive.org/web/20220819024741/https://github.com/topics/axi4-lite
Here are
16 public repositories
matching this topic...
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Aug 17, 2022
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SystemVerilog
Basic USB 1.1 Host Controller for small FPGAs
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Audio controller (I2S, SPDIF, DAC)
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Sep 1, 2019
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Verilog
AXI4 and AXI4-Lite interface definitions
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Sep 20, 2020
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SystemVerilog
An AXI4 crossbar implementation in SystemVerilog
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May 9, 2022
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SystemVerilog
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Jun 5, 2021
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Verilog
Master and Slave made using AMBA AXI4 Lite protocol.
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Oct 9, 2020
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Stata
Multi-port BRAM IP for ASIC and FPGA
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Apr 21, 2021
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SystemVerilog
VHDL generator from SystemRDL
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Updated
Jun 19, 2021
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Python
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
OLED driver demo running on ZedBoard
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021
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Verilog
Hardware implementation of a base 2 logarithm
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Sep 15, 2021
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Jupyter Notebook
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