axi4-lite

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Here are 16 public repositories matching this topic...

pulp-platform / axi

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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Aug 17, 2022
SystemVerilog

ultraembedded / core_usb_host

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Basic USB 1.1 Host Controller for small FPGAs

fpga usb usb-host axi4-lite ulpi utmi

Updated Jun 6, 2020
C

OSVVM / AXI4

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AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component

Updated Aug 8, 2022
VHDL

ultraembedded / core_audio

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Audio controller (I2S, SPDIF, DAC)

audio fpga verilog dac i2s axi4-lite spdif

Updated Sep 1, 2019
Verilog

mmxsrup / axi4-interface

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AXI4 and AXI4-Lite interface definitions

fpga systemverilog axi4 axi4-lite axi4-stream

Updated Sep 20, 2020
SystemVerilog

dpretet / axi-crossbar

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An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 9, 2022
SystemVerilog

ultraembedded / core_usb_bridge

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USB -> AXI Debug Bridge

fpga usb verilog usb-cdc axi4-lite

Updated Jun 5, 2021
Verilog

somyadashora / AMBA-AXI4-Lite

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Master and Slave made using AMBA AXI4 Lite protocol.

design verilog amba axi4-lite

Updated Oct 9, 2020
Stata

ic-lab-duth / NoCpad

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HLS for Networks-on-Chip

hls noc high-level-synthesis network-on-chip cache-coherence axi4 axi4-lite

Updated Feb 18, 2021
C++

dpretet / meduram

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Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

MicroTCA-Tech-Lab / hectare

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VHDL generator from SystemRDL

fpga vhdl systemrdl axi4-lite

Updated Jun 19, 2021
Python

krailis / zynq-axi-tutorial

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A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)

tcl vivado petalinux high-level-synthesis axi4-lite amba-axi axi4-stream-interfaces

Updated Jul 15, 2016
Tcl

zdzislaw-s / oled-driver-demo

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OLED driver demo running on ZedBoard

c-plus-plus sdk zynq hardware animation freertos verilog spi vivado ssd1306 oled-display zedboard xilinx-fpga xilinx-vivado bitstream oled-display-ssd1306 axi4-lite

Updated Jun 24, 2018
PHP

CSpyridakis / Reconfigurable-Computing

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Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

fpga zynq hls vhdl xilinx vivado vivado-hls zynq-7000 evaluation-board rsoc axi4 axi4-lite reconfigurable-computing axi4-protocol axi4-stream-protocol

Updated Oct 13, 2020
C++

rlee287 / hardware-bus-infrastructure

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A collection of formal properties for hardware buses, and cores using them.

psl sva wishbone-bus axi4 axi4-lite axi4-stream bus-standards

Updated Feb 22, 2021
Verilog

Gabriele-bot / Base2_Log

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Hardware implementation of a base 2 logarithm

fpga python3 verilog logarithm lookup-table axi4-lite

Updated Sep 15, 2021
Jupyter Notebook

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