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Here are 296 public repositories matching this topic...

SpinalHDL / VexRiscv

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A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Jan 18, 2023
Assembly

TheresAFewConors / Sooty

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The SOC Analysts all-in-one CLI tool to automate and speed up workflow.

python dns security workflow automation analysis phishing hash cybersecurity soc security-automation analysts urlscan reputation-check proofpoint-decoder soc-analysts

Updated Dec 13, 2022
Python

stnolting / neorv32

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🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga core processor vhdl gdb riscv rtos soc risc-v openocd soft-core system-on-chip rv32 neorv32 riscof

Updated Feb 2, 2023
VHDL

ucb-bar / chipyard

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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Feb 3, 2023
C

deepfence / PacketStreamer

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⭐ ⭐ Distributed tcpdump for cloud native environments ⭐ ⭐

pcap secops suricata packet-sniffer network-analysis soc hacktoberfest observability traffic-monitoring packet-capture zeek snort security-tools tcpdump-like infosectools forensics-tools

Updated Jan 30, 2023
Go

riscv-mcu / e203_hbirdv2

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The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203

Updated Dec 10, 2022
Verilog

xboot / xboot

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The extensible bootloader for embedded system with application engine, write once, run everywhere.

mtk lua os boot embedded-systems operating-system rockchip samsung bootloader soc freescale allwinner xboot application-engine

Updated Jan 29, 2023
C

sergeykhbr / riscv_vhdl

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Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

debugger qt simulator cpu vhdl riscv systemc soc

Updated Jan 31, 2023
Verilog

tenzir / vast

Sponsor

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🔮 Visibility Across Space and Time – The network telemetry engine for data-driven security investigations.

security netflow pcap network-forensics incident-response actor-model bitmap-index pipelines dataops suricata siem sigma soc zeek investigation threathunting secdataops

Updated Feb 3, 2023
C++

TonyPhipps / SIEM

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SIEM Tactics, Techiques, and Procedures

Updated Dec 28, 2022

TonyPhipps / Meerkat

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A collection of PowerShell modules designed for artifact gathering and reconnaisance of Windows-based endpoints.

Updated Jan 16, 2023
PowerShell

Xilinx / Vitis_Accel_Examples

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Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Jan 30, 2023
Makefile

satan1a / TheRoadOfSO

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学习安全运营的记录 | The knowledge base of security operation

wiki cybersecurity knowledge-base soc threat-analysis security-analysis security-operations security-operation

Updated Sep 3, 2022
HTML

WangXuan95 / USTC-RVSoC

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An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

cpu fpga riscv rtl verilog systemverilog soc risc-v rv32i softcore

Updated Nov 26, 2022
SystemVerilog

stnolting / neo430

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💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

open-source microcontroller fpga processor vhdl gcc customizable msp430 soc soft-core system-on-chip msp430-gcc

Updated Nov 23, 2021
VHDL

eshlomo1 / Microsoft-Sentinel-SecOps

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Microsoft Sentinel SOC Operations

microsoft security azure incident-response secops threat-hunting siem hunting soc ir cloudsecurity threat-intelligence azure-sentinel microsoft-sentinel

Updated Nov 10, 2022
PowerShell

rggen / rggen

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Code generation tool for configuration and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Jan 27, 2023
Ruby

ui-model / ui-model

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UI Model major repository

react library angular reuse soc ui-model no-comonent

Updated Jan 4, 2023
TypeScript

Patrowl / PatrowlHears

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PatrowlHears - Vulnerability Intelligence Center / Exploits

Updated Jan 18, 2023
Python

cyb3rxp / awesome-soc

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A collection of sources of documentation, as well as field best practices, to build/run a SOC

architecture detection management incident-response soa cert csirt siem tip soc risk-management ttp soar sirp mitre-attack purpleteam

Updated Jan 9, 2023

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