VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

Pinned

OpenRAM Public

An open-source static random access memory (SRAM) compiler.

Python 499 148
openram-docker-image Public

Shell 4 2
openram-vagrant-image Public

Settings to build a Vagrant image for OpenRAM

Shell 3 2

OpenRAM Public
An open-source static random access memory (SRAM) compiler.

Python 499 BSD-3-Clause 148 20 6 Updated Mar 16, 2023
vlsida-eda Public
Conda recipes for VLSIDA projects.

Shell 2 BSD-3-Clause 0 0 0 Updated Jan 31, 2023
openram_testchip2 Public

Verilog 0 Apache-2.0 0 0 0 Updated Jan 5, 2023
sky130_sram_macros Public

SourcePawn 3 Apache-2.0 3 0 0 Updated Dec 20, 2022
sky130_fd_bd_sram Public

0 Apache-2.0 0 0 0 Updated Nov 19, 2022
sky130-validation Public
Silicon validation projects for SKY130 stuff

C++ 0 BSD-3-Clause 2 0 0 Updated Nov 18, 2022
gf180_fd_bd_sram Public

1 0 0 0 Updated Oct 31, 2022
openram_testchip Public
https://caravel-user-project.readthedocs.io

Verilog 5 Apache-2.0 266 0 0 Updated Oct 10, 2022
VLSIDA Public

0 0 0 0 Updated Sep 12, 2022
klayout Public
klayout tech files

Ruby 0 1 0 0 Updated Aug 3, 2022

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