lowRISC / opentitan
OpenTitan: Open source silicon root of trust

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OpenTitan: Open source silicon root of trust
Simple single-port AXI memory interface
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SystemVerilog modules and classes commonly used for verification
AXI X-Bar
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs