analogdevicesinc / hdl
HDL libraries and projects
| Jan | FEB | Mar |
| 04 | ||
| 2022 | 2023 | 2024 |

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HDL libraries and projects
The USRP™ Hardware Driver Repository
ECE 5745 Tutorial 4: Synopsys/Cadence ASIC Tools
Wraps the NVDLA project for Chipyard integration
Plugins for Yosys developed as part of the F4PGA project.
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.