pulp-platform / hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system

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IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
OpenTitan: Open source silicon root of trust
Pipelines the AXI path with FIFOs
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
AXI X-Bar
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Generic Register Interface (contains various adatpers)
open-source Ethenet media access controller for Ariane on Genesys-2
Simple single-port AXI memory interface
APB Timer Unit