microarchitecture

Open-source high-performance RISC-V processor

A cross platform C99 library to get cpu features at runtime.

Simple yet fancy CPU architecture fetching tool

How to exploit a double free vulnerability in 2021. Use After Free for Dummies

inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques

Microarchitectural exploitation and other hardware attacks.

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser

Achieve peak performance on x86 CPUs and NVIDIA GPUs

FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation

High performance Bitcoin development platform

A small RISC-V core (SystemVerilog)

A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)

Performance Counter Measurements at the cycle granularity

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog

CPU micro benchmarks

One Instruction Set Computer

Custom 64-bit pipelined RISC processor