processor-design

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Here are 35 public repositories matching this topic...

darklife / darkriscv

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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu fpga core processor riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Oct 7, 2022
Verilog

katef / eurorack-cpu

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A CPU implemented in a modular synthesizer

modular synthesizer cpu-emulator processor-design

Updated Mar 20, 2022

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

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Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

alirezakay / RISC-CPU

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A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jun 19, 2021
VHDL

shehanmunasinghe / tinyGPU

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A Predicated-SIMD processor implementation in SystemVerilog

gpu simd systemverilog hdl computer-organization processor-design

Updated Jul 14, 2021
SystemVerilog

AnkurRyder / 8085-Processor

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8-bit RISC Processor on Logisim

circuit-simulator logisim processor-design

Updated Oct 1, 2020

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

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EE577b-Course-Project

verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal

Updated May 6, 2020
Verilog

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

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CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

computer-science processor-architecture engineering computer-engineering textbooks computer-organization computer-organisation processor-design computer-organisation-architechure computer-organization-lab computer-organization-and-design computer-organ ameythakur amey

Updated Jun 3, 2022
C

LeviBohnacker / EDRICO

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EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and implement modern processor architectures.

embedded risc-v 32-bit processor-design risc-vcore

Updated Jul 19, 2021
VHDL

lazyoracle / vhdl-processor

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An 8-bit processor in VHDL based on a simple instruction set

processor-architecture fpga processor vhdl verilog vivado hardware-designs hdl xilinx-fpga processor-simulator hardware-description-language digital-electronics altera-fpga processor-design

Updated Mar 7, 2019
VHDL

JayKaku / RISC-V_MYTH_Workshop

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RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

riscv microprocessor computer-architecture vlsi risc-v tlv riscv32 processor-design riscv32i computer-hardware

Updated Apr 29, 2022
Python

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

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Domain Specific Hardware Accelerators - VLSI CAD Project

processor-architecture ram hardware processor bus bluespec hardware-designs vlsi hardware-acceleration vlsi-physical-design bluespec-systemverilog processor-design vector-processor vlsi-design bluespec-systemverilog-language vlsi-cad

Updated Jan 11, 2021
Bluespec

kara-abdelaziz / SEP-CPU

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SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

processor-architecture cpu processor computer-architecture digital-design computer-organization processor-design processor-simulation

Updated Aug 31, 2021
Assembly

Bennyaw / SimpleProcessor_Verilog

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A simple processor designed using Verilog and Altera DE1 development board.

simple modelsim verilog-hdl quartus processor-design altera-de1

Updated Apr 22, 2020
Verilog

0xD503 / ARM-Single-Cycle-Processor

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ARM architecture single-cycle processor designed according to book "Digital design and computer architecture: ARM edition" as a practice in digital design.

processor-architecture arm embedded model-simulation processor-design

Updated Jun 27, 2019
SystemVerilog

overengineer / SpecialPurposeProcessor

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FPGA implementation of a special purpose processor that performs single operation using custom ALU. You can take look at the [related blog post] (https://overengineer.github.io/SpecialPurposeProcessor) for further details.

fpga verilog processor-design

Updated Jan 3, 2019
Verilog

rj45 / nanogo

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NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs

go golang cpu compiler assembly hobby-project hobby-compiler processor-design hobby-language homebrew-computer

Updated Jan 4, 2022
Go

daniel-santos-7 / leaf

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Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

fpga riscv fpga-soc risc-v wishbone-bus processor-design

Updated Oct 20, 2022
VHDL

Subangkar / Computer-Architecture-CSE-306-BUET

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Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET