artix-7

Here are 30 public repositories matching this topic...

ultraembedded / biriscv

Sponsor

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

ultraembedded / FPGAmp

Sponsor

Star

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

fpga mjpeg hdmi sd-card motion-jpeg rtos vga risc-v jpeg-decoder ir-codes artix-7 fpga-media-player hd-video

Updated Nov 21, 2020
C

ZAP is a High Performance ARMV5TE Compatible Superpipelined Processor with Caches, MMUs and TLBs that is capable of reaching 160MHz@Artix-7 FPGA. ZAP is Copyright (C) 2016-2022 Revanth Kamaraj. Released under the GNU GPL v2 license.

Updated Dec 25, 2022
SystemVerilog

ultraembedded / usb2sniffer

Sponsor

Star

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

fpga usb rtl verilog wireshark xilinx-vivado usb-debugging usb-scanning artix-7 usb2 usb-analyzer usb-sniffer lambdaconcept-usb2sniffer-hardware

Updated Jun 6, 2020
Verilog

Mario-Hero / Async-Karin

Star

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

fpga async asynchronous verilog cyclone-iv asynchronous-framework artix-7 async-karin async-circuit

Updated Dec 14, 2020
Verilog

j3soon / Handwritten-Digit-Recognition-Painter

Star

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

deep-learning hardware verilog basys3 painter artix-7

Updated Dec 19, 2019
VHDL

liolok / HDU_CO_Guide

Star

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

verilog vivado computer-organization course-design artix-7

Updated May 13, 2019
Verilog

michaelriri / 16-bit-risc-processor

Star

A 16-bit Reduced Instruction Set Computing(RISC) processor capable of fetching and executing a set of 16-bit machine instructions.

fpga verilog risc artix-7

Updated Oct 1, 2017
Verilog

raleighlittles / Applied_Digital_Logic_Exercises_Using_FPGAs

Sponsor

Star

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

fpga verilog vivado hdl basys3 artix-7 microblaze-mcs applied-digital-logic-exercises

Updated Jan 12, 2022
Verilog

vankxr / icyradio

Sponsor

Star

Over-engineered SDR development board

Updated Nov 30, 2022
VHDL

chipsalliance / f4pga-xc-fasm2bels

Star

Library to convert a FASM file into BELs importable into Vivado.

tcl verilog vivado fasm bitstream artix-7 symbiflow

Updated Jul 22, 2022
Verilog

tuhalf / SOMvhdl

Star

A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.

data-science data-mining fpga vhdl som kohonen-map self-organizing-map arty artix-7

Updated Jan 31, 2021
VHDL

SnrNotHere16 / FPGADivisionFloatingPoint

Star

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)