The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

Verilog 675 239 Built by

0 stars today

Star

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

Verilog 603 205 Built by

1 star today

Star

EttusResearch / uhd

The USRP™ Hardware Driver Repository

Verilog 726 576 Built by

2 stars today

Star

YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 2,192 587 Built by

1 star today

Star

Xilinx / libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

Verilog 106 43 Built by

1 star today

Star

google / CFU-Playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

Verilog 316 77 Built by

0 stars today

Star

alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

Verilog 1,288 440 Built by

0 stars today

Sponsor

Star

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

Verilog 660 148 Built by

1 star today

Star

ashutoshaks / COA-Laboratory-CS39001

Assignments for the Computer Organization And Architecture Laboratory course

Verilog 5 Built by

Star

qrp73 / ali_trx

Building your own SDR DDC/DUC transceiver with DIY modules from aliexpress

Verilog 12 2 Built by

0 stars today

Star

chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Verilog 55 34 Built by

0 stars today

Star

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Verilog 752 264 Built by