alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
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efabless / caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
google / CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
pranav-nb / verilog_tutorial
This repo is basically where I dump all my verilog code used in my verilog course.
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
lnis-uofu / OpenFPGA
An Open-source FPGA IP Generator
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
The-OpenROAD-Project / OpenROAD-flow-scripts
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
aolofsson / oh
Verilog library for ASIC and FPGA designers
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
IObundle / iob-mem
Verilog behavioral description of various memories
ericlewis / openFPGA-Genesis
FPGA implementation of Sega Genesis for Analogue Pocket.
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
nand2mario / nestang
NESTang is a Nintendo Entertainment System emulator on the affordable Sipeed Tang Primer 20K FPGA board.
enjoy-digital / litepcie
Small footprint and configurable PCIe core
ucb-bar / nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
