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hdl
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During the work on merging #1419 I figured out that the basic BUFGMUX example works differently on Arty Board and Nexys Video.
The example uses three LEDs:
- led[2] - blinks with slow frequency
- led[1] - blinks with high frequency
- led[0] - blinks with the same frequency as led[2] or led[1] depending on sw[0] state.
On the Arty Board, the example works as intended. On Nexys Video, when
Here are some "nice to have" feature requests for the cool new "Compared test results" output that has been recently added.
- Colors! It would be nice to highlight;
- Improvements in green
- Regressions in red.
- Non-changes de-emphasized in light grey.
- Link to the published version of the before and after results so people can understand exactly
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It would be nice if the Hardware Description Languages section mentioned simulating tooling like:
- iverilog
- gtkwave
- verilator
A few things that I wish I learned from the workshop rather that "discovering/googling" by myself:
- use iverilog as a linter (seems to be more pedantic that yosys).
- how to create testbench
- how to
$monitorvariable - gotcha to create / optimize vhd fi
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Jun 28, 2022 - Verilog
Together with issue #4, we should write a few tests for making sure refdeses do stay consistent. Something like a copy of servo_micro, and a ton of patches on top of it (all parented to one servo_micro, not on a chain, more like a star). Apply each of those patches then see if refdeses are sticking.
git checkout c718fbc~1 examples/servo_micro.py from google/pcbdl@ba3
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Motivation
It doesn't make sense for a signal to be driven by two drivers in a
Sequentialblock. The code already prevents this, but testing is incomplete.Desired solution
Add a test ensuring that an exception is thrown when there are multiple drivers for a flop.