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BrianHG-DDR3-Controller Public
Forked from DECAfpga/BrianHG-DDR3-Controller
DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included.
SystemVerilog 1
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deca-mandelbrot Public
Forked from amaranth-community-unofficial/deca-mandelbrot
The Terasic DECA board as a mandelbrot acceleerator
Python 1
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nanorv32 Public
Forked from rbarzic/nanorv32
A small 32-bit implementation of the RISC-V architecture
Verilog
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